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RadiSys EPC-3311 Hardware Reference Manual

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  • Page 1 (217) 352-9330 | Click HERE Find the RadiSys EPC-3311 at our website:...
  • Page 2 ® -3311 Hardware Reference 007-01289-0005 • November 2003 www.radisys.com Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 Copyright ©2003 by RadiSys Corporation. All rights reserved. EPC and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ, MultiPro, SAIB, Spirit, and ValuePro are trademarks of RadiSys Corporation. DAVID, MAUI, OS-9, OS-9000, and SoftStax are registered trademarks of RadiSys Microware Communications Software Division, Inc.
  • Page 4 Description Introduction Introduces the EPC-3311 and briefly describes its features and functions. Installation and operation Explains how to install the EPC-3311 in a CompactPCI mainframe. BIOS configuration Explains how to configure the BIOS using the built-in BIOS setup menus. Theory of operation...
  • Page 5 RadiSys web site • World Wide Web: RadiSys maintains an active site on the World Wide Web. The site contains current information about the company and locations of sales offices, new and existing products, contacts for sales, service, and technical support information.
  • Page 6 About related RadiSys products 82600 High Performance System Controller A member of the RadiSys family of long-life embedded PC compatible core logic. the 82600 is a highly integrated single chip implementation of all requirements of a high performance Compact PCI Central Resource and Peripheral Bridge including the North Bridge, South Bridge, PCI to PCI Bridge, and a selected set of Super I/O †...
  • Page 7 ® -3311 Hardware Reference ESM/EFM-31xx blades Single-slot CompactPCI PICMG 2.16 compliant Layer 2 and Layer 3 switches that feature 24 Fast Ethernet link ports, 4Gb up-links, and integrated platform management. Other PICMG CompactPCI specification, PICMG. For information about PICMG and the CompactPCI standard, consult the PICMG website at this URL: http://www.picmg.org PCI architecture...

  • Page 8: Table Of Contents

    Operation ............................14 Powering on the system ......................14 Hot insertion/Hot swapping ....................... 15 Post-installation troubleshooting ...................... 15 Maintaining and upgrading the EPC-3311..................15 Extracting the EPC-3311......................15 Dis-assembling the EPC-3311 ....................16 Replacing the battery ....................... 16 Installing other options ......................17 Re-assembling the EPC-3311 .....................
  • Page 9 Chapter 5: Theory of operation Organization............................. 50 Block diagram ..........................50 Features ............................51 CPU ............................51 RadiSys 82600 ........................... 51 Power-up configuration ....................... 51 Host bridge.......................... 52 Memory subsystem ......................52 PCI interrupts ........................53 Dual PCI bus architecture ....................53 IDE ............................
  • Page 10 Contents Optional board-mounted accessories..................63 Hard disk drives......................... 63 Hard disk drive options ....................... 63 IDE disks ..........................64 Ultra DMA .......................... 64 Chapter 6: RTMs Features ............................66 Installation and configuration......................67 Before you begin ........................67 Inserting the RTM........................68 Removing the RTM ........................
  • Page 11 Index 04—Reset Event register (0x04) ..................114 Index 05—Local Interrupt Control/Status register (0x05) ............115 Index 06—Reset Control register (0x06) ................... 116 EPC-3311 General Purpose Control register (0x07) ..............117 Index 08—Boot ROM Access Control register (0x08) .............. 118 Index 09—Reserved register (0x09) ..................119 Index 0A—ROM Program Control register (0x0A) ..............
  • Page 12 Figure 3-11. Boot menu........................... 39 Figure 3-12. Exit menu..........................41 Figure 4-1. MBA menu..........................46 Figure 5-1. EPC-3311: block diagram ..................... 50 Figure 6-1. RTMs: block diagram ......................69 Figure 6-2. RTM: connectors ........................70 Figure C-1. Flash chip memory addresses....................89 Figure D-1.
  • Page 13 Table 7-4. User LED ..........................80 Table 7-5. Hot Swap LED........................80 Table 7-6. IPMI FRU inventory area ....................... 81 Table A-1. EPC-3311 I/O map ........................ 83 Table A-2. EPC-3311 memory map ......................84 Table A-3. Fixed I/O-mapped ports and registers ..................85 Table B-1.

  • Page 14: Figure 1-1. The Epc-3311

    CompactPCI system. • Optional rear transition module: A rear I/O transition module which plugs into a rear I/O slot of a CompactPCI system. The EPC-3311 can operate with either the RTML or the RTM216. Figure 1-1. The EPC-3311 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 15 You cannot install a Processor PMC (such as the EPC-6315) the PMC A/B site when a CompactFlash is installed. • IDE devices. The EPC-3311 supports a maximum of two IDE devices connected to the processor board or the RTM. For information about the IDE connectors, Appendix D, Connectors Chapter 6, RTMs.

  • Page 16: Features

    BIOS/Flash ROM device of 4 MB. • EPC-3311 CompactPCI bus configuration: • When installed in a system slot, the EPC-3311 functions as a system controller. • When installed in a peripheral slot, the EPC-3311 functions as a peripheral processor. •...

  • Page 17: External Interfaces

    Injector/ejector levers (with a hot swap micro switch). External interfaces The EPC-3311 has external interfaces available from the front panel, the CompactPCI standard connectors J1-J5, and onboard interfaces. The RTM offers more connectors for the functions on the main board.

  • Page 18: Specifications

    Mobile Intel Pentium III Processor-M with a 133 MHz front side bus. • 1200 MHz. • Micro FC–BGA package. Chipset RadiSys 82600 chipset (North bridge and P2P bridge). Cache 512 KB Level 2 write-back cache operating at full clock speed. Memory •...

  • Page 19: Environmental

    The EPC-3311 meets the following environmental specifications with no hard disk drive installed: • The EPC-3311 is for use only with compatible UL Listed computers that have installation instructions detailing user installation of card cage accessories. • The operating environment must provide sufficient airflow (300 LFM) across the board to keep it within its temperature specification.

  • Page 20: Additional Specifications

    300 LFM airflow at a maximum ambient temperature of 55 °C. ¹ The EPC-3311’s mechanical outline complies with IEEE 1101.1, 1101.11, and P1101.11 mechanical requirements. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 21 ® -3311 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 22 Installation and operation Chapter 2 Before using the EPC-3311, you need to determine how you want to install the board, install peripherals, and set switches and jumpers. This chapter explains how. To install or configure options for the EPC-3311, see the appropriate appendix: •...

  • Page 23: Before You Begin

    The EPC-3311, like most other electronic devices, is susceptible to ESD damage. ESD damage is not always immediately obvious. It can cause a partial breakdown in semiconductor devices that might not result in immediate failure.

  • Page 24: Setting Jumpers And Headers

    Chapter 2: Installation and operation Setting jumpers and headers Figure 2-1. EPC-3311: jumper locations ROM_TOP (J7) Manufacturing header (J4) POST header (P1) ROM_TOP (J7) H8 Programming header (J8) Manufacturing header (J4) Figure 2-2. Manufacturing header settings Enables writes to the ROM’s lower 512KB in...

  • Page 25: Rom_Top (J7)

    ® -3311 Hardware Reference ROM_TOP (J7) Figure 2-3. ROM_TOP jumper settings Moves the System BIOS Moves the System BIOS to the flash chip’s upper to the flash chip’s lower 512KB of the top 1MB. 512KB of the top 1MB. For more information about the ROM, see Appendix I, Re-programming the flash chip.

  • Page 26: Post Header (P1)

    2. Insert the EPC-3311 into the chassis subrack with the card edges in the card guide rails and carefully push the EPC-3311 into the chassis subrack until the CompactPCI connectors engage the connector body at the backplane.

  • Page 27: Operation

    2. Turn the power to your system on. If there is no power, Check all power connections and the power source. System management can direct the EPC-3311 to remain unpowered. Ensure that any system management applications are properly configured to allow the board to power up.

  • Page 28: Hot Insertion/Hot Swapping

    2. Move the ejector handles to the eject position: push the top handle up and the bottom handle down so that the handles appear tilted. 3. Slide the EPC-3311 module out of its slot. Pull firmly on the handles to release the module from the connectors.

  • Page 29: Dis-Assembling The Epc-3311

    ® -3311 Hardware Reference 4. If your EPC-3311 includes an option, disassemble the board as described in Dis-assembling the EPC-3311. Dis-assembling the EPC-3311 To separate an option board from the main board: 1. Remove the EPC-3311 in the chassis as described in Extracting the EPC-3311.

  • Page 30: Installing Other Options

    Chapter 2: Installation and operation 6. Press the new battery into place, positive (+) side up. Note: The battery will not discharge voltage if installed backwards. 7. If your EPC-3311 includes an option, re-assemble the board as described in Re-assembling the EPC-3311.

  • Page 31: Peripheral Devices

    • The USB bus supports up to 127 USB devices, which can be attached in a daisy-chain configuration. • The EPC-3311 supports one USB controller on the RTM panel. • A single USB cable cannot exceed 5 meters (16.4 feet) in length.

  • Page 32: Chapter 3: Bios Configuration

    Boot menu on page 39. BIOS setup screens The EPC-3311’s BIOS includes a setup program that displays and modifies the system configuration. The EPC-3311’s nonvolatile CMOS RAM stores configuration information, and the BIOS uses it to initialize the EPC-3311 hardware.

  • Page 33: Navigation

    ® -3311 Hardware Reference Select from the menus shown in the next table to set up the BIOS. Menu Sub-menu Main Setup menu IDE Configuration sub-menu Primary Master/Slave sub-menus Console Redirection sub-menu Boot Options sub-menu Keyboard Features sub-menu Advanced menu Advanced Chipset Control sub-menu PCI Configuration sub-menu PCI/PNP ISA IRQ Resource Exclusion sub-menu...

  • Page 34: Main Setup Menu

    Chapter 3: BIOS configuration Main Setup menu Figure 3-1. BIOS Main Setup menu PhoenixBIOS Setup Utility Main Main Advanced Boot Exit System Time: [16:17:18] Item Specific Help System Date: [01/01/2002] <Tab>, <Shift-Tab>, or <Enter> selects field. IDE Configuration Console Redirection Boot Options Keyboard Features System Memory:...

  • Page 35: Ide Configuration Sub-Menu

    -3311 Hardware Reference Field Description BIOS version Displays the EPC-3311 System BIOS version. This field is not editable; no user interaction is required. Crisis Reflash version Displays the EPC-3311 Crisis Reflash program version. If the program is not installed, this field displays "none".
  • Page 36 Chapter 3: BIOS configuration On-board hard disk Determines whether the onboard HDD or 2.5" or 2.5" HDD drive is a Master or Slave device. This option toggles the IDE CSEL (cable select) signal to only the on-board devices. A CompactFlash device always relies on the state of CSEL to tell whether it is a Master or Slave.

  • Page 37: Primary Master/Slave Sub-Menus

    • Auto (default): Select this option when you want the POST to query the hard disk for its parameters whenever the POST runs. RadiSys recommends this option. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 38 Chapter 3: BIOS configuration Field Description Type Note: If you set a hard disk to “Auto” but no hard disk is (cont’d) actually present, the BIOS queries the (non-existent) hard disk until it times out, slightly increasing the duration of the POST. •...
  • Page 39 ® -3311 Hardware Reference Field Description Multi-Sector Transfers Allows the System BIOS to read ahead by the specified number of sectors during disk access. This has the effect of reading more data at once to reduce the absolute number of discrete disk reads performed by the operating system, which may increase system performance.
  • Page 40 Chapter 3: BIOS configuration Field Description Transfer Mode The fast DMA modes take full advantage of the onboard (cont’d) bus mastering hard disk controller and should yield the highest performance when used in conjunction with multitasking operating systems that support it. Notes: •...

  • Page 41: Console Redirection Sub-Menu

    ® -3311 Hardware Reference Console Redirection sub-menu Figure 3-4. Console Redirection sub-menu PhoenixBIOS Setup Utility Main Main Console Redirection Item Specific Help Console Redirect Port [On-board COM A] <Tab>, <Shift-Tab>, or <Enter> selects field. Console Redirection Baud Rate:[38.4K] Console Type [VT100] Flow Control [None]...

  • Page 42: Boot Options Sub-Menu

    Chapter 3: BIOS configuration Console connection You can select one of these: • Direct (default) • Via modem Continue C.R. after POST Determines the state of console redirection after POST. You can select one of these: • On (default): Leaves console redirection turned on at the end of POST.
  • Page 43 ® -3311 Hardware Reference Field Description QuickBoot Mode You can select one of these: • Enabled (default): Allows the SBC to skip certain tests while booting. This decreases the time needed to boot the SBC. • Disabled: Runs all tests during boot. Summary screens Determines whether the system configuration displays prior to loading the operating system.

  • Page 44: Keyboard Features Sub-Menu

    Chapter 3: BIOS configuration Keyboard Features sub-menu Options on this menu set and change keyboard settings. Figure 3-6. Keyboard Features sub-menu PhoenixBIOS Setup Utility Main Main Keyboard Features Item Specific Help NumLock: [Auto] <Tab>, <Shift-Tab>, or <Enter> Keyboard auto-repeat rate: [30/sec] selects field.

  • Page 45: Advanced Menu

    ® -3311 Hardware Reference Advanced menu This menu contains settings for integrated peripherals, memory shadow, cache, and large disk access mode. You access this menu by selecting Advanced from the Main BIOS Setup menu. Figure 3-7. Advanced menu PhoenixBIOS Setup Utility Main Main Advanced...
  • Page 46 Chapter 3: BIOS configuration Field Description Installed OS Identifies the OS you plan to use on this system. You can select one of these: • Other (default): Select this option when you plan to use an OS other than Windows 95, Windows 98 or Windows 2000.

  • Page 47: Advanced Chipset Control Sub-Menu

    Save and Exit Field Description ECC Config Determines the state of the RadiSys 82600’s ECC circuitry. You can select one of these: • Enabled (default): The 82600 corrects and writes back single-bit ECC errors. The generation of ~BSERR on multiple-bit errors and NMI on single-bit errors is a feature of the 82600, but is left disabled by the BIOS.
  • Page 48 Watchdog Reload Controls the RadiSys 82600 watchdog timer. At boot time, the BIOS sets the DGCTRL, Watchdog Control/Status Register: A=PWRBASE+1A, R=00 to the value of 0x3D, which causes a reload on the 82600 LDEV0 or LDEV1 (local device decodes) or 82600 assertion of ~BDEVSEL or ~BFRAME.

  • Page 49: Pci Configuration Sub-Menu

    ® -3311 Hardware Reference PCI Configuration sub-menu Use the options in this sub-menu for PCI. Figure 3-9. PCI Configuration sub-menu PhoenixBIOS Setup Utility Main Advanced PCI Configuration Item Specific Help PCI IRQ line 1: [Auto Select] <Tab>, <Shift-Tab>, or <Enter> PCI IRQ line 2: [Auto Select] selects field.
  • Page 50 Chapter 3: BIOS configuration Field Description Backplane Ready Determines whether resources are exported to the backplane. This is accomplished via the 82600 BPCI Ready bit. You can select one of these: • Enabled (default): Does not export resources to the CompactPCI (BPCI) bus.

  • Page 51: Pci/Pnp Isa Irq Resource Exclusion Sub-Menu

    ® -3311 Hardware Reference PCI/PNP ISA IRQ Resource Exclusion sub-menu The PCI/PNP ISA IRQ Resource Exclusion Sub-Menu controls the exclusion of PCI and ISA interrupt regions. Figure 3-10. PCI/PNP ISA IRQ Resource Exclusion sub-menu PhoenixBIOS Setup Utility Main Main Advanced Boot Exit PCI/PNP ISA IRQ Resource Exclusion...

  • Page 52: Boot Menu

    Chapter 3: BIOS configuration Boot menu The Boot menu controls the order of the available boot devices. Items that display on this screen depend on installed hardware and user selections. If you make changes in this menu, do not make changes in the Configuration sub-menu.
  • Page 53 Options Field Description Removable Devices Because the EPC-3311 does not support legacy floppy drives, this option has no effect. Hard Drive Specifies the order in which POST installs devices, assigning device number 80h to the first device, 81h to the second, and so on.

  • Page 54: Exit Menu

    Chapter 3: BIOS configuration Exit menu Options in this menu save and exit, or abandon your changes and exit to the system. Figure 3-12. Exit menu PhoenixBIOS Setup Utility Main Exit Main Advanced Boot Exit Saving Changes Item Specific Help Exit Discarding Changes <Tab>, <Shift-Tab>, or <Enter>...
  • Page 55 ® -3311 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 56: Chapter 4: Mba Configuration

    † The EPC-3311 includes an emBoot , Inc. MBA (Managed PC Boot Agent), a client- based firmware which allows the EPC-3311 to perform network booting. MBA supports the PXE (Preboot Execution Environment) network boot protocol and † additional boot protocols such as BOOTP, DHCP, RPL, and NCP/IPX(Netware It is an integrated component of the EPC-3311 Flash EEPROM.

  • Page 57: Mba Features

    See the appropriate chapter of this guide for your network protocol. When you turn on the EPC-3311, the following occurs: • The EPC-3311 System BIOS performs its usual initial tests and setup, such as a memory test. • The MBA displays this configuration message.

  • Page 58: Navigation

    MBA to verbose mode by pressing and holding the v key or Ctrl+Alt before MBA begins to execute. On the EPC-3311 you can do this during the long pause that follows the memory test. Release the key(s) once MBA has started to execute Shift + Shift Displays MBA information.

  • Page 59: Mba Configuration Options

    ® -3311 Hardware Reference MBA configuration options Figure 4-1. MBA menu Managed PC Boot Agent (MBA) v5.50 (BIOS Integrated) (C) Copyright 1999–2002 3Com Corporation (C) Copyright 2002 emBoot Incorporated All rights reserved Configuration Boot Method: TCP/IP Protocol: DHCP Config Message: Enabled Message Timeout: Boot Failure Prompt:...
  • Page 60 Chapter 4: MBA configuration Field Description Config Message Determines whether the MBA displays a message that tells the user which keys to press to access the MBA Configuration Screen. Valid values include: • Enabled (default): Displays this message: Press Ctrl+Alt+B to configure… •...
  • Page 61 ® -3311 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 62 Theory of operation Chapter 5 The EPC-3311, a 6U single-slot board, plugs into either a system or peripheral slot of a CompactPCI backplane. It can be used with either a 2.16 compliant or a non-2.16 backplane. When reading this file online, you can immediately view information about any EPC-3311 topic by placing the mouse cursor over the topic name and clicking: For information about...

  • Page 63: Organization

    ® -3311 Hardware Reference Organization Block diagram The next figure shows the division and interconnection of EPC-3311 functions. The following sections provide detailed descriptions of these items. Figure 5-1. EPC-3311: block diagram PMC A PMC B Optional CompactFlash 2.5" HDD...

  • Page 64: Features

    Chapter 5: Theory of operation Features The foundation of the EPC-3311’s design consists of the Mobile Intel Pentium III Processor-M (Tualatin) with the RadiSys 82600 system controller and the connection to CompactPCI J1, J2, and J3. RadiSys 82600 The RadiSys 82600 high integration dual PCI system controller functions as a combination north bridge, a super I/O, and a PCI-CompactPCI bridge.

  • Page 65: Host Bridge

    ® -3311 Hardware Reference ADDR7: Selection of general-purpose I/O pins or COM1 function. COM1 (Default). General-purpose I/O, DIO [25..31] ADDR8: Sets the I/O Queue depth. Queue depth is 8 (default). Queue depth is 1. ADDR10 and ADDR11: Combination determines the PSB frequency: ADDR10 ADDR11 Mode...

  • Page 66: Pci Interrupts

    PCI configuration space access must be made with the device's corresponding IDSEL address bit set. • PCI device detail For all PCI buses on the EPC-3311, the following table summarizes the allocation of IDSEL, Request/Grant pair, and Interrupt(s) for each device. Table 5-1. PCI devices IDSEL...
  • Page 67 PCI interface to the FPGA. The FPGA does not require bus arbitration signals. With the EPC-3311, much of the chassis status (e.g., board ID and shelf address) is accessed through the HMC. The features and functions of the EPC-3311 assigned to its FPGA include: •...
  • Page 68 FPGA configuration header is cleared (CFG Reg 04, bit 02). When memory space is disabled, the FPGA signals this by negating its ~MEM_EN output. The EPC-3311 may use this signal to force the boot ROM device into a low power state.

  • Page 69: Ide

    System battery The EPC-3311 utilizes a CR2032 lithium (Li/MnO 2 ) coin battery. This +3V battery provides power to retain the correct date, time, and computer parameters in CMOS when the system is powered off. This information assists the BIOS in performing initialization and configuration during power-on or reset operations.

  • Page 70: Hot Swap And System Management

    Read Write Hot Swap and system management The EPC-3311 meets the requirements for Full Hot Swap as defined by the CompactPCI Hot Swap specification. The EPC-3311 can functions as: • A host processor by occupying a system slot in a CompactPCI backplane which may or may not have a 2.16 compliant interconnection fabric.

  • Page 71: High Availability

    The RadiSys-managed HA implementation recognizes, emulates, and coexists with the high availability signals defined in PICMG 2.1. However, the activation of those signals only occurs when the EPC-3311 is installed in a chassis which implements, elsewhere in the system, the centralized, proprietary control logic required to implement PICMG 2.1 HA Hot Swap.

  • Page 72: Ipmi Management System

    +3.3V, +5V, +12V, and –12V domains. The backplane also provides IPMB_PWR for the system management subsystem; this potential may be active when the main power rails are not. The EPC-3311 implements appropriate isolation between the HMC and the rest of the board to comply with the PICMG 2.9 System Management Specification on system...

  • Page 73: System Management Power

    EPC-3311 must have ~BD_SEL cycle by external HA circuitry, or by removing and reinserting the board. When the EPC-3311 is in the connected state, peak current is as follows: • +3.3V: 8 Amps maximum. This limitation is based on a 1 amp per pin current limit (PICMG 2.1, Sec.

  • Page 74: Hmc Hardware Watchdog

    Chapter 5: Theory of operation HMC hardware watchdog The HMC implements a software-enabled watchdog as defined in the IPMI specification. This watchdog can generate a board reset to recover from the host processor’s failure. This configurable watchdog is started by software commands from the host processor.

  • Page 75: Optional Features

    • One PS/2-style combination mouse and keyboard port. The PS/2 port on the EPC-3311’s I/O bracket is configured by default for use with a PS/2 keyboard. To use this port with a PS/2 mouse also, you must first attach a “Y” splitter cable.

  • Page 76: Optional Board-Mounted Accessories

    A single SDRAM memory module board may be attached to the EPC-3311. Memory modules are available in 512 MB, and 1 GB sizes. • Three optional devices can physically mount in the top section of the EPC-3311: • One 2.5" hard disk drive •...

  • Page 77: Ide Disks

    IDE device. The IDE channel is connected to local devices on the EPC-3311 only, or is connected to the RTM only. The EPC-3311, along with its RTM, can house four devices, but because the IDE channel supports only two devices, invalid IDE configurations are possible.
  • Page 78 Chapter 6 This chapter describes the EPC-3311’s optional RTMs (Rear Transition Modules): • EPC-3311 RTML: This board features one PMC I/O site and two RJ-45 100/1000Base-T Ethernet connectors. The RTML works with the EPC-3311 and a non-packet-switched backplane in a chassis.

  • Page 79: Features

    ® -3311 Hardware Reference Features The RTMs, optional, single-slot 6U CompactPCI peripherals, provide connectors that get I/O out the back of a chassis: • Two RJ-45 100/1000Base-T Ethernet connectors with LEDs for link and activity (RTML only). • A 44-pin, straight male IDE header that provides a connection point for a hard-disk ribbon cable.

  • Page 80: Installation And Configuration

    5. • A chassis such as the RadiSys CP50. To install the RTM onto a passive backplane not manufactured by RadiSys, consult the instructions provided by the backplane manufacturer. • An already-installed EPC-3311. For information about installing the EPC-3311, Chapter 2, Installation and operation.

  • Page 81: Inserting The Rtm

    You cannot hot-swap the RTM. 2. Locate the slot on the rear of the backplane directly opposite the EPC-3311. 3. Ensure that the ejector handles are in the normal (non-eject) position. (Push the top handle down and the bottom handle up so that the handles are not tilted.)

  • Page 82: Block Diagram

    Chapter 6: RTMs Block diagram Figure 6-1. RTMs: block diagram RTML RTM216 Faceplate Faceplate Backplane Backplane DB-9 DB-9 USB1 USB1 KBD/ KBD/ mouse mouse ENET 1 PMC-A Port 0 RJ45 Rear I/O ENET 2 Port 1 RJ45 PMC-B PMC-B Rear I/O Rear I/O Artisan Technology Group - Quality Instrumentation ...

  • Page 83: Rtm Connectors

    ® -3311 Hardware Reference RTM connectors Connector locations The next figure shows the locations of connectors on the EPC-3311 RTM: Figure 6-2. RTM: connectors RTML RTM216 RS-232 DE-9 connector USB connector Link/activity LEDs Ethernet connectors PIM connector Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 84: Compactpci Connectors (J3 And J5)

    Chapter 6: RTMs CompactPCI connectors (J3 and J5) The RTM uses two {platform} connectors, J3 and J5. J5 connector J5 provides the connection for all T1/E1 pairs and LED control from PMC connector Jn4. J5 also provides connection paths between the RTM and the TDM2IX and the CPLD.

  • Page 85: J3 Connector

    ® -3311 Hardware Reference J3 connector The J3 connector is a user-defined connector that routes T1/E1 and Ethernet signal pairs and LED controls to the RTM for specific use with the 8-port Serial 2-port Ethernet RTM. J3 provides the interface for PCI Ethernet signaling and LED control as well as IX Ethernet signaling and LED control.

  • Page 86: Ethernet Connectors

    In a legacy (non-2.16) chassis, these signals pass through to RJ-45 connectors on the RTM. • The EPC-3311 does not support the 82544’s Wake-On-LAN and TCO interfaces. The Ethernet connector is used on the EPC3311-RTML. The EPC3311-RTM216 has an additional PIM socket in place of the Ethernet connectors.

  • Page 87: Ide Header (Internal)

    Ground Mouse clock The EPC-3311 keyboard and mouse pins are opposite the laptop industry standard. This allows a keyboard to plug in directly without “Y” splitter adapter. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 88: Pim Connector

    Chapter 6: RTMs PIM connector The EPC-3311 supports two 32-bit PCI 5 V I/O-compatible PMC sites on the board. Each PMC site uses three PMC connectors. • Jn1 and Jn2 carry the standard PCI signals and power. • Jn4 signals are routed through the backplane to the RTM PIM site(s).

  • Page 89: Rs-232 De-9 Connector

    ® -3311 Hardware Reference Table 6-8. PIM connector pin assignments (Continued) Pn0/Jn0 Pn4/Jn4 Signal –12V Signal Signal +12V and –12V are not connected on the RTM. Pn4/Jn4 pins correspond to the Jn4 pins of the PMC. RS-232 DE-9 connector Table 6-9. RS-232 RTM connector Signal Signal No connect...

  • Page 90: Chapter 7: Hardware Management

    Remote hardware management also cuts response time for these functions. IPMI (Intelligent Platform Management Interface), used to implement hardware management on the EPC-3311, defines a standard protocol as well as a standard hardware interface for instrumentation. Overview An independent management controller provides local hardware management services on the EPC-3311.

  • Page 91: Local Management Services

    Sensor monitoring The HMC monitors the health of the EPC-3311 on which it resides. EPC-3311 health is determined by the monitoring of sensors located throughout the board, which range from on-board voltage readings to ambient temperatures. The next table lists local sensors that the HMC monitors.

  • Page 92: Controls

    EPC-3311 faceplate. The LED, labeled "Blade", indicates the Healthy state of the HMC and EPC-3311. A green LED indicates that the board is healthy and that no faults exist. A red LED indicates that the board is not healthy and that a fault does exist.

  • Page 93: Status Leds

    Status LEDs The HMC also provides access to a second LED that indicates the status of software executing on the EPC-3311. This LED, located just above the HW LED and labeled “User”, indicates the Health of the software. Table 7-4. User LED...

  • Page 94: Sel (System Event Log)

    Chapter 7: Hardware management Table 7-6. IPMI FRU inventory area Area Contents Comments Board • Manufacturing date/time Board area information is defined within the scope of the firmware and contains • Board manufacturer valid default values. The Board area is •...
  • Page 95 ® -3311 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 96: Appendix A: Chipset And I/O Map

    Chipset and I/O map Appendix A I/O map Table A-1. EPC-3311 I/O map I/O address (hex) Register description DMA controller 1 – 8237A 0000 – 000F Master 8259A 0020 – 0021 Power management 0022 8254A timer/counter 0040 - 0043 Keyboard controller data and control registers (if enabled)

  • Page 97: Memory Map

    The memory map shows the location of the standard DRAM, VGA, and BIOS devices. The table below describes how physical addresses from the † Mobile Tualatin map into memory. Table A-2. EPC-3311 memory map Range CPU address Region Cached 0 to 640 KB DRAM (640 KB) 0000 0000 –...

  • Page 98: Pci I/O Space

    In addition, a pair of these registers is used to access a set of index-mapped registers for RadiSys-specific status and control. The direct I/O-mapped registers are in the table below. The default values shown for these registers are loaded after a POR (Power on Reset).
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  • Page 100: Appendix B: Interrupts

    Interrupts Appendix B The next table shows interrupt assignments for the EPC-3311. Table B-1. Interrupts Interrupt Generic Interrupt function capable IRQ0 System timer (internal 82600 connection) IRQ1 Keyboard controller (internal 82600 connection) IRQ2 Cascade interrupt input (internal 82600 connection) IRQ3 COM2 (not used;...
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  • Page 102: Appendix C: Flash Memory Addresses

    Flash memory addresses Appendix C The EPC-3311 4MB flash chip contains these major sections: Figure C-1. Flash chip memory addresses System address Byte offset in 4MB port 0xFFFF FFFF 003F FFFF System BIOS (0.05 MB) Reflash program (0.05 MB) 0xFFF0 0000...
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  • Page 104 Connectors Appendix D This appendix details the connectors on the EPC-3311 and gives the signal pinout of each connector. For more information about connectors on rear transition modules, see Chapter 6, RTMs. This product includes the connectors listed in the table below. When reading this file online, you can immediately view information about any connector by placing the mouse cursor over a connector name and clicking.

  • Page 105: Connector Locations

    ® -3311 Hardware Reference Connector locations Figure D-1 shows the locations of the connectors on the EPC-3311’s CPU board. For information about installing peripherals and jumper settings, see Configuration and installation. Figure D-1. EPC-3311 connector locations Jn2 connector IDE header (internal)

  • Page 106: Compactpci Connectors

    The backplane determines which voltage by its VIO connection to one of these power supplies. The EPC-3311 uses VIO as its power source for its drivers and pull-ups. Because the EPC-3311 is a universal board, no coding key is used in the J1 connector.

  • Page 107: J1 Connector

    ® -3311 Hardware Reference J1 connector The CompactPCI J1 connector is a female 2mm-pitch 6 column by 25 row right angle Hard Metric (HM) connector with a guide lug in the center. Table D-1. CompactPCI J1 connector ~REQ64 ~ENUM +3.3V AD[1] AD[0] ~ACK64 GND...

  • Page 108: J2 Connector

    Appendix D: Connectors J2 connector The CompactPCI J2 connector is a female 2mm-pitch 6 column by 22 row right angle Hard Metric (HM) connectorCompactPCI J2 Connector Table D-2. CompactPCI J2 connector CLK6 CLK5 ~ALERT BRSV BRSV BRSV BRSV BRSV ~PRST ~REQ6 ~GNT6 BRSV...

  • Page 109: J3 Connector

    ® -3311 Hardware Reference J3 connector The J3 connector is a user-defined connector that routes T1/E1 and Ethernet signal pairs and LED controls to the RTM for specific use with the 8-port Serial 2-port Ethernet RTM. J3 provides the interface for PCI Ethernet signaling and LED control as well as IX Ethernet signaling and LED control.

  • Page 110: J5 Connector

    Appendix D: Connectors J5 connector J5 provides the connection for all T1/E1 pairs and LED control from PMC connector Jn4. J5 also provides connection paths between the RTM and the TDM2IX and the CPLD. The four connections, labeled CAP:RTMn and CPLD:RTMn respectively, are reserved;...

  • Page 111: Pmc Connectors

    ® -3311 Hardware Reference PMC connectors Jn1 connector Table D-5. Jn1 connector (PMC 32-bit PCI interface) Signal Signal No connect No connect No connect No connect No connect :~BUSMODE1 (Low) No connect No connect +3.3V LPCI:CLK PC/PCIDMA~GNT PC/PCIDMA~REQ No connect LPCI:AD[31] LPCI:AD[28] LPCI:AD[27]...

  • Page 112: Jn2 Connector

    Appendix D: Connectors Jn2 connector Table D-6. Jn2 connector (PMC 32-bit PCI interface) Signal Signal No connect No connect No connect No connect No connect No connect No connect SIRQ ~BUSMODE2 (N/C) +3.3V LPCI:~RST ~BUSMODE3 (N/C) +3.3V ~BUSMODE4 (N/C) No connect LPCI:AD[30] LPCI:AD[29] LPCI:AD[26]...

  • Page 113: Serial Port

    -3311 Hardware Reference Serial port This connector is used on the I/O panels of both the EPC-3311 main board and on the EPC3311-RTML. The pin signals for the EPC-3311 connector are listed in the next table. The pin signals for the EPC-3311-RTML and EPC-3311-RTM216 are...

  • Page 114: Ide Header (Internal)

    IDE header (internal) The secondary IDE connector is a male 44-pin 2x22, 0.1" pitch connector located on the EPC-3311 which provides a connection point for a hard-disk ribbon cable. The pins and signals are defined as: Table D-8. Primary IDE connector...

  • Page 115: Compactflash Socket

    ® -3311 Hardware Reference CompactFlash socket Table D-9. CompactFlash socket pinout Signal Type Signal Type Ground –CD1 -CE1 –CE2I –VS1 Ground –IORD –IOWR –WE RDY/BSY Power Power –CSEL –VS2 RESET –WAIT –INPACK –REG BVD2 BVD1 –CD2 Ground Ground Reset button The reset is a momentary push-button recessed switch.

  • Page 116: Table E-1. Post Message Codes

    Messages Appendix E This appendix lists the Phoenix BIOS 4.06 standard POST error codes which can generate console messages. Table E-1. POST message codes Class Number Name Disk errors 200h ERR_DISK_FAILED Keyboard errors 210h ERR_KBD_STUCK 211h ERR_KBD_FAILED 212h ERR_KBD_KCFAIL 213h ERR_KBD_LOCKED Video errors 220h...
  • Page 117 ® -3311 Hardware Reference Table E-1. POST message codes Class Number Name I/O errors 2E0h ERR_IO_ADDRESS 2E1h ERR_IO_COM 2E2h ERR_IO_LPT 2E3h ERR_IO_CONFLICT 2E4h ERR_IO_UNSUPPORTED 2E5h ERR_IO_IRQ 2E6h ERR_IO_IDE 2E7h ERR_IO_FDD Other errors 2F0h ERR_OTHER_CPUID 2F1h ERR_OTHER_BIST 2F2h ERR_OTHER_BSP 2F3h ERR_OTHER_AP 2F4h ERR_OTHER_CMOS 2F5h...

  • Page 118: Appendix F: Pmc Modules

    PMC slot PMC modules Appendix F The EPC-3311 supports either one or two PCI mezzanine card (PMC) modules for a variety of task processing applications. You cannot install a Processor PMC (such as the EPC-6315) the PMC A/B site when a CompactFlash is installed.

  • Page 119: Disconnecting The Pmc Module

    You can install only one device in each PMC slot. When an HDD is installed in slot A, you cannot install a PMC in that slot. 3. Remove and save the blank face plate from the PMC slot in the EPC-3311 face plate.

  • Page 120: Figure F-2. Removing A Pmc Module

    Appendix F: PMC modules To separate the PMC module and the main board: Figure F-2. Removing a PMC module 1. Remove the EPC-3311 from the CompactPCI chassis as described in Extracting the EPC-3311 on page 15. 2. Remove screws on the back of the main board.
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  • Page 122: Appendix G: Compactflash Cards

    CompactFlash slot CompactFlash cards Appendix G The CompactFlash card is located on the EPC-3311 beneath the PMC “A” or hard disk drive slot. • The CompactFlash card must be installed before installing a PMC or a hard drive in the PMC “A” slot.

  • Page 123: Figure G-1. Inserting A Compactflash Card

    ® -3311 Hardware Reference 3. If your EPC-3311 includes an option and it prevents you from accessing the CompactFlash socket, disassemble the board as described in Dis-assembling the EPC-3311 on page 16. 4. Locate the CompactFlash socket on the board.

  • Page 124: Appendix H: Fpga Features Register Set

    IRQ_EN Reset En IRQ_EN Interrupt Control/Status Index 06— RSVD PRST_SEL RSVD HMC_SEL FP_SEL SYS_EN CPCI_SYS ITP_SEL 0x06 _SEL Reset Control EPC-3311 General RSVD RSVD LATCH ENUM RSVD RSVD Flash_Size[1..0] 0x07 Purpose Control Index 08—Boot ROM 0x08 Seg_ Seg_ Seg_ RSVD...

  • Page 125: Bios Control/Status Register (0X100)

    ® -3311 Hardware Reference BIOS Control/Status register (0x100) IDE_RST ISO_RTM HDD_ ~HDD_ ~CF_ ROM_ RSVD RSVD 0x100 Master Present Present Access: – – – IDE_RST A read/write bit that asserts the output ~IDE_RST low when set to 1. ISO_RTM Routes the EIDE bus. Values for this read/write bit include: Routes to local devices.

  • Page 126: Fpga Rsi (Register Set Index) Register (0X185)

    Appendix H: FPGA features register set FPGA RSI (Register Set Index) register (0x185) NDX0 0x185 RSVD RSVD RSVD RSVD NDX3 NDX2 NDX1 Access: RSVD Reserved for future use. These read-only bits always return a 0 (zero). NDX[3..0] Selects the active FPGA Features register. The combined NDX bits provide this 4-bit index register.

  • Page 127: Index 04-Reset Event Register (0X04)

    Front panel reset asserted. Front panel reset did not assert. CPCI_SYS Indicates whether the EPC-3311, when configured as a peripheral, receives a reset from the system controller. Values for this read/write-clear bit include: The system controller reset the board.

  • Page 128: Index 05-Local Interrupt Control/Status Register (0X05)

    ISA IRQ the PCI interrupt is routed to by examining bits 3:0 of the RadiSys 82600 LIRQRC[D] Route Control Register at PCI configuration space offset 0xA3 of device 0 function 0. For detailed information about this register, see the 82600 High Integration Dual PCI System Controller Databook.

  • Page 129: Index 06-Reset Control Register (0X06)

    CPCI_SYS_SEL Determines what occurs when a system controller reset asserts. Used only when the EPC-3311 is a peripheral. Values for this read/write bit include: An IBR_IRQ (IBR interrupt request). Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 130 Appendix H: FPGA features register set A board reset. ITP_SEL Determines what occurs when an ITP reset asserts. Values for this read/write bit include: An IBR interrupt request (IBR_IRQ). A board reset. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 131: Epc-3311 General Purpose Control Register (0X07)

    ® -3311 Hardware Reference EPC-3311 General Purpose Control register (0x07) RSD7 RSD6 RSD5 RSD4 RSD3 RSD2 RSD1 RSD0 0x07 RSVD RSVD LATCH ENUM RSVD RSVD Flash_Size[1..0] Access: LATCH Identifies the front panel latch state. Values for this read-only bit include: The front panel eject handle is closed.

  • Page 132: Index 08-Boot Rom Access Control Register (0X08)

    When the 82600 forwards memory accesses to the PCI bus, this register controls decoding of the alias region to a memory location in the ROM. The RadiSys 82600 must be properly set for this to occur. For more information about the 82600, see the 82600 High Performance System Controller.
  • Page 133 ® -3311 Hardware Reference Index 09—Reserved register (0x09) RSD7 RSD6 RSD5 RSD4 RSD3 RSD2 RSD1 RSD0 0x09 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Access: RSVD Reserved for future use. These read-only bits always return a 0 (zero). Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 134: Index 0A-Rom Program Control Register (0X0A)

    Appendix H: FPGA features register set Index 0A—ROM Program Control register (0x0A) BIOS_WE BB_WEN RSVD RSVD RSVD RSVD RSVD 0x0A PGM_EN Access: BIOS_WE Determines access for the upper 512KB of the ROM’s top 1MB. Values for this read/write bit include: Does not allow write access to the upper 512KB.
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  • Page 136: Appendix I: Re-Programming The Flash Chip

    Perform Crisis Reflash from serial port ............... 128 Perform Crisis Reflash from LS-120 drive............130 About the flash chip The EPC-3311 flash chip contains these sections: Figure I-1. Flash chip memory addresses • BIOS: Initializes the hardware and finds a device from which to bootload.

  • Page 137: Figure I-2. Flash Chip Re-Programming Coverage

    ® -3311 Hardware Reference The rest of the flash chip is available for customer use. For more information, contact RadiSys as described in Where to get more information on page iv. For details about the flash chip’s sections, including addresses, see...

  • Page 138: Selecting A Re-Programming Method

    Selecting a re-programming method When re-programming the flash chip, use this flowchart to determine which process to use. Be sure to read Before you begin Obtain files from RadiSys pages 124 and 125 before going to the page indicated below. Re-programming...

  • Page 139: Before You Begin

    • (Optional) A RadiSys POST card. The EPC-3311 has a 14-pin female header, P1, which accepts a RadiSys POST card, a small PCB with two seven-segment LEDs that display the status sent to legacy PC I/O port 80h. Both phlash.exe and the BIOS send status to this port.

  • Page 140: Obtain Files From Radisys

    Appendix I: Re-programming the flash chip • Update the Crisis Reflash program: Use this method if the existing BIOS runs. RadiSys recommends this as the simplest method. This process is not supported on a non-DOS OS (for example: Windows NT, QNX).
  • Page 141 16-bit DOS program. It cannot be used from a 32-bit Microsoft Windows command line. It has been tested on the EPC-3311 in three DOS-compatible environments. You can start phlash.exe from the serial redirection console, but the serial redirection feature may not display the graphics of phlash.exe completely.

  • Page 142: Update The Bios Program

    • (Optional, but recommended) An installed VGA PMC. • (Optional) An installed RadiSys POST card. 2. Ensure that memory managers such as HIMEM.SYS, EMS, XMS or DPMI are not loaded. To boot without loading memory managers, press F5 just before DOS starts.

  • Page 143: Perform Crisis Reflash From Serial Port

    2. Disconnect IDE devices from the EPC-3311. This program works in the presence of some IDE devices, but not all configurations have been tested. 3. Connect the cable between the host system and the EPC-3311’s Serial Reflash RS-232 port. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 144 For more information about this jumper, see ROM_TOP (J7) on page 12. 8. Power-up or reset the EPC-3311. The Crisis Reflash program runs. After you start the Serial Reflash, this sign-on message, which originates from the EPC-3311 Crisis Reflash program (not the host system software), displays: RadiSys Flash Recovery Console, Version EPC-3311 1.0...

  • Page 145: Perform Crisis Reflash From Ls-120 Drive

    BIOS in the sign-on screen or BIOS Setup Main menu. Perform Crisis Reflash from LS-120 drive The EPC-3311 Crisis Reflash Program can boot and reflash from 1.44MB floppy diskette inserted in an IDE LS-120 Superdrive installed on either the on-board IDE connector or the RTM IDE connector.
  • Page 146 BIOS Version N.MM.LL Where N.MM.LL is the version number from README.TXT. 5. Boot the Crisis Reflash Diskette on the EPC-3311: A. Connect these J7 pins to activate the Crisis Reflash program: You must jumper pins 2 and 3 to activate the Crisis Recovery program...

  • Page 147: Dos Restrictions

    FreeDOS is available from http://www.freedos.org. The kernel and basic utilities are under GPL2 licence. See the site for more detail. Installation is from 1.44MB floppy media. The EPC-3311 BIOS bootloads from a 1.44MB floppy media installed in an LS-120 Superdrive IDE bus.

  • Page 148: Glossary

    Glossary (American National Standards Institute) An organization dedicated to ANSI advancement of national standards related to product manufacturing. (AT Bus Attachment) An interface definition for PC peripherals. See IDE. An Advanced Technology Attachment drive, also known as an IDE drive, is a hard- drive with the interface built-in.
  • Page 149 ® -3311 Hardware Reference operating system loads, the computer performs a general hardware initialization and resets internal registers. The storage device from which the computer boots the operating system. Boot device The order in which a computer searches external storage devices for an operating Boot sequence system to boot.
  • Page 150 Glossary applied, unless the data are periodically rewritten into memory during a refresh operation. A software component of the operating system which directs the computer Driver interface with a hardware device. The software interface to the driver is standardized such that application software calling the driver requires no specific operational information about the hardware device.
  • Page 151 ® -3311 Hardware Reference number and pattern of pins which corresponds to the number and pattern of sleeves on a female header plug. (Hardware Management Controller) Describes the hardware common to the Baseboard management Controller and the Satellite Management Controller. The HMC provides the ability to monitor, quesry and log system management events on the {product name short} and in the CompactPCI system.
  • Page 152 Glossary Copying information from an extension ROM into DRAM and accessing it in this Memory shadowing alternate memory location. The difference in location of memory-mapped data between the physical address Offset and the logical address. (Operating System) See DOS. PC/AT (Personal Computer/Advanced Technology) A popular computer design first introduced by IBM in the early 1980s.
  • Page 153 ® -3311 Hardware Reference (Preboot Execution Environment) The PXE specification (part of the Intel Wired for Management initiative) has become the standard definition of protocols and interfaces required for network booting. (Random Access Memory) Memory in which the actual physical location of a memory word has no effect on how long it takes to read from or write to that location.
  • Page 154 Glossary segment is the portion of a real mode address which specifies the fixed base address to which the offset is applied. Sensor Event Log. A physical connection with a computer for the purpose of serial data exchange with Serial port a peripheral device.
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  • Page 156: Index

    CompactFlash logical, defined socket physical, defined CompactPCI real mode, defined specification Advanced menu CompactPCI connectors ANSI, defined EPC-3311 architecture, dual PCI bus architecture, PCI assembling the board autotype, defined battery replacing configuration BIOS byte, defined data area, defined...
  • Page 157 LEDs controllers extended Ethernet memory memory, defined controls system configuration data block conventional memory, defined extension, BIOS conventions, notational extracting the EPC-3311 CP50 chassis crisboot.bin crisdisk.bat fault annunciation Crisis Reflash program features version, identifying hardware management Cylinders/Heads/Sectors (CHS), defined optional...
  • Page 158 Hot Swap FRU inventory area high availability host interface Hot Swap with EPC-3311 in peripheral slot sensor monitoring with EPC-3311 in system slot status LEDs system event log watchdog logical address, defined disks hard disk type...
  • Page 159 EPC-3311 devices, configuring the RTM interrupts replacing the battery system controller re-programming flash chip PCI/PNP ISA IRQ Region Exclusion Sub-Menu obtaining files from RadiSys Pentium III re-programming the flash chip peripherals explained connecting requests phlash.exe IRQ, defined...
  • Page 160 Secondary Master sub-menu flash, defined Secondary Slave sub-menu upgrades sensor monitoring URLs serial port connector PCI SIG setting jumpers and headers RadiSys sockets, CompactFlash USB connector static-sensitive devices, handling USB controller status LEDs User LED Strataflash device USR LED support...

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