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RadiSys EPC-5A Hardware & Software Reference Manual

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EPC
-5A
Hardware & Software
Reference Manual
RadiSys Corporation
5445 NE Dawson Creek Drive
Hillsboro, Oregon 97124
Phone: (503) 615-1100
Fax: (503) 615-1150
http://www.radisys.com
____________________________________________________________________
07-0870-01
October 1998

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  • Page 1 ® Hardware & Software Reference Manual RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro, Oregon 97124 Phone: (503) 615-1100 Fax: (503) 615-1150 http://www.radisys.com ____________________________________________________________________ 07-0870-01 October 1998...
  • Page 2 EPC-5A Hardware & Software Reference Manual EPC, iRMX, INtime, Inside Advantage and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma and SAIB are trademarks of RadiSys Corporation. All other trademarks, registered trademarks, service marks, and trade names are the property of their respective owners.
  • Page 3 If an EPC product fails to operate in compliance with its specification during this period, RadiSys will, at its option, repair or replace the product at no charge. The customer is, however, responsible for shipping the product; RadiSys assumes no responsibility for the product until it is received.

  • Page 4: Table Of Contents

    EPC-5A Hardware & Software Reference Manual Table of Contents 1. Product Description ....................1 Purpose........................1 About this Manual....................1 Notational Conventions..................2 Product Overview....................3 Specifications ......................4 Differences Between EPC-5 and EPC-5A.............4 2. Before Installation ....................7 Configuring the EPC-5A ..................7 Selecting the EPC-5A Slot Location ..............8 Installing the VMEbus Backplane Jumpers............10...
  • Page 5 EPC-5A Hardware & Software Reference Manual Advanced Menu ....................37 EXM Menu......................39 VME Menu......................42 Exit Menu......................44 5. Theory of Operation ....................47 Processor board .....................47 Processor and Coprocessor ................47 Core Logic......................47 Memory ......................48 Memory Map ....................48 Peripheral Components ..................50 Real Time Clock....................50 Keyboard Controller....................51...
  • Page 6 EPC-5A Hardware & Software Reference Manual Parallel Port......................88 Keyboard .......................88 Speaker Header .....................89 Battery Header ......................89 8. Upgrades........................91 Memory.........................91 9. Troubleshooting & Error Messages ..............93 Troubleshooting ....................93 Common Error Messages ..................95 Boot Failures ......................101 Phoenix™ NuBIOS Checkpoints ................102 10. Support and Service....................107 In North America ....................107...
  • Page 7 Figure 2-1. Slot-1 Jumper Location ................8 Figure 2-2. Daisy-Chain Signal Concept ............... 10 Figure 2-3. Backplane Jumpers Required for EPC-5A Subsystem ........ 11 Figure 2-4. VMEbus Backplane Jumper Examples ............12 Figure 2-5. VMEbus Jumpers on Rear Wirewrap Pins ..........13 Figure 2-6.
  • Page 8 EPC-5A Hardware & Software Reference Manual List of Tables Table 1-1. EPC-5A Environmental and Electrical Specifications........4 Table 2-1. VME Slots Available..................9 Table 2-2. EPC-5A Jumpers ..................13 Table 5-1. R400EX Features ..................48 Table 6-1. Direct Mapping..................... 59 Table 7-1.

  • Page 9: Product Description

    This manual was written to provide detailed hardware reference information for OEMs, system integrators, and other engineers using the EPC-5A as a component of their VMEbus systems. The reader should be able to install the EPC-5A and configure the system based on the information in this manual.

  • Page 10: Notational Conventions

    Connectors. Describes pinouts for the serial and parallel port connectors, plus the keyboard, speaker, and battery headers. Chapter 8 Upgrades. Lists possible memory upgrades for the EPC-5A. Chapter 9 Troubleshooting and Error Messages. Describes various error conditions and recovery procedures.

  • Page 11: Product Overview

    The EPC-5A form factor has been designed to the VMEbus specification (6U). It provides direct communication to all three VMEbus address spaces (A32, A24, & A16). The EPC-5A DRAM permits dual-ported access from both the PC side and the VME side.

  • Page 12: Specifications

    EPC5A. Table 1-1. EPC-5A Environmental and Electrical Specifications. Differences Between EPC-5 and EPC-5A The EPC-5A differs from the EPC-5 in the following ways: The System BIOS is based on Phoenix Technologies NuBIOS revision 4.05. The EPC-5 uses an Award BIOS.
  • Page 13 Chapter 1: Product Description Support for “User BIOS Extensions” which allows, through BIOS extensions, booting from VME or EXM-2A, etc. Note that EXM-2A’s are supported while the EXM-2 is not. The System BIOS supports disk autotyping and disks larger than 528MB capacity.
  • Page 14 EPC-5A Hardware & Software Reference Manual NOTES Page 6...

  • Page 15: Before Installation

    The Slot-1 configuration option is enabled (default) by installing the Slot-1 shunt (jumper) on the processor board (see Figure 1, page 4). Removing the jumper disables Slot-1 functionality. When the EPC-5A is configured as the Slot-1 controller, it performs all the standard VMEbus system control functions. See Chapter 5, Theory of Operation, for more details on Slot-1 controller functions.

  • Page 16: Selecting The Epc-5A Slot Location

    Additionally, the EPC-5A has another jumper (see Figure 2-1 above) that rarely needs to be changed - the MODID jumper on JP1. The EPC-5A uses pin 30, Row A of the P2 connector for module identification. If the J2 backplane is other than a standard VME or VXI backplane (e.g., a VSB backplane) or Pin 30, Row A is defined for...

  • Page 17: Table 2-1. Vme Slots Available

    Chapter 2: Before Installation The EPC-5A plus EXM expansion modules plus any mass storage module can be considered together as a single subsystem. Use the following worksheet to determine the total number of VME expansion interface slots your particular subsystem configuration requires.

  • Page 18: Installing The Vmebus Backplane Jumpers

    EPC-5A Hardware & Software Reference Manual Installing the VMEbus Backplane Jumpers The VMEbus specification provides four bus grant signals ( ) and one interrupt acknowledge signal ( IACK ) via daisy-chain lines. Per the VMEbus specifications, all boards (that plug into the backplane) are required to correctly handle these signals.

  • Page 19: Figure 2-3. Backplane Jumpers Required For Epc-5A Subsystem

    Figure 2-3. Backplane Jumpers Required for EPC-5A Subsystem. The figure above shows the EPC-5A subsystem. Note that the left-most slot does not require any jumpers. All other slots occupied by the subsystem require all five jumpers be installed.

  • Page 20: Figure 2-4. Vmebus Backplane Jumper Examples

    EPC-5A Hardware & Software Reference Manual IACK "Dumb" Slave Single Board Computer Does not handle that only handles IACK & BG3 any of the signals Figure 2-4. VMEbus Backplane Jumper Examples. Once you have determined where the jumpers need to be, you must determine how to jumper your particular backplane.

  • Page 21: Figure 2-5. Vmebus Jumpers On Rear Wirewrap Pins

    Chapter 2: Before Installation J1 Connectors J1 Connector IACK IACK Figure 2-6. VMEbus Jumpers Figure 2-5. VMEbus Jumpers on Front Stake Pins. on Rear Wirewrap Pins. If the stake pins are on the rear of the backplane, the most common location is in the middle of the J1 connector as shown in Figure 2-5 below.

  • Page 22: Jumpers

    EPC-5A Hardware & Software Reference Manual Jumpers The complete table of EPC-5A jumpers is shown below. Jumpers are shown in Figure 2-1. Jumper Function Description POST Manufacturing loop Install this jumper to enter the (JP1 [1-2]) enable manufacturing POST loop.

  • Page 23: Installation

    CAUTION During all of this installation process, make sure that power to your system is OFF. The EPC-5A is not designed to be inserted or removed while the chassis is powered up. CAUTION Make sure that the installation process described here is performed in a static-free environment.

  • Page 24: Exp-Bp2 Subplane

    EPC-5A Hardware & Software Reference Manual EXP-BP2 Subplane This subplane is used in the smallest configuration, where only the EPC-5A processor module occupies VME slot space. It provides connectivity for two EXM modules within the EPC-5A (e.g., a graphics controller and a network or disk controller).

  • Page 25: Exp-Bp4 Subplane

    Chapter 3: Installation EXP-BP4 Subplane The EXP-BP4 subplane is used to couple an EPC-5A processor module with an EXP-MX Mass Storage module. The EXP-BP4 is a T-shaped board with four connectors on the front side and three on the rear.

  • Page 26: Exp-Bp3A Subplane

    EPC-5A Hardware & Software Reference Manual EXP-BP3A Subplane The EXP-BP3A subplane is used to add an EXP-MC Module Carrier for the addition of one or two more EXM modules to an EPC-5A processor module. The EXP-BP3A has five connectors on each side.

  • Page 27: Exp-Bp5 Subplane

    Chapter 3: Installation EXP-BP5 Subplane The EXP-BP5 subplane is used in a configuration to couple an EPC-5A processor module with an EXP-MC Module Carrier and an EXP-MX Mass Storage module. The EXP-BP5 has six connectors on the front side and five on the rear.

  • Page 28: Exp-Bp4A Subplane

    EPC-5A Hardware & Software Reference Manual EXP-BP4A Subplane The EXP-BP4A subplane is used to add either • two EXP-MC Module Carriers • one EXP-AM Adapter Module. The EXP-BP4A has seven connectors on each side. After jumpering the backplane, plug the...

  • Page 29: Exp-Bp6 Subplane

    Chapter 3: Installation EXP-BP6 Subplane The EXP-BP6 subplane is used in a configuration to couple an EPC-5A processor module with an EXP-MX Mass Storage module and either • two EXP-MC Module Carriers • one EXP-AM Adapter Module. The EXP-BP6 has eight connectors on the front side and seven on the rear.

  • Page 30: Epc-5A Insertion

    EPC-5A Hardware & Software Reference Manual EPC-5A Insertion After installing the subplane, the EPC-5A processor module can be inserted into the VMEbus chassis. CAUTION Make sure that power to your VME system is off. The EPC-5A module is not designed to be inserted or removed from a live backplane.

  • Page 31: Exp-Mc Module Carrier Insertion

    If one or more EXP-MC Module Carriers are part of the configuration, they are inserted into the slot(s) immediately to the right of the EPC-5A. The Module Carrier can only be used in a VMEbus slot where the subplane has both EXM connectors.

  • Page 32: Exp-Mx Mass Storage Module Insertion

    EXM Module Insertion One or two EXMs may be installed through the front panels of the EPC-5A and each EXP-MC Module Carrier. To install an EXM: Remove and save the blank face plate from the desired slot.

  • Page 33: Connecting Peripherals To The Epc-5A

    PCs, and is not compatible with the previous style of larger 5-pin PC/AT keyboard connectors. However, an adapter cable is provided with the EPC-5A so either type of PC keyboard can be used with the EPC-5A.

  • Page 34: Serial Ports

    The front panel contains two DB-9 DTE serial-port connectors. They are standard RS-232 serial communication ports that are 16C450-compatible. Many current PC/AT computers now incorporate 16C550 UARTs. The EPC-5A serial ports may be used for connecting a mouse, modem, serial printer, RS-232 link, etc. Parallel Printer Port...

  • Page 35: Bios Configuration

    BIOS Setup Screens The EPC-5A’s BIOS contains a setup function to display and modify the system configuration. This information is maintained in the EPC-5A’s nonvolatile CMOS RAM and is used by the BIOS to initialize the EPC-5A hardware.

  • Page 36: Figure 4-1. Bios Setup Menu Map

    EPC-5A Hardware & Software Reference Manual Main BIOS Setup Menu EXIT MAIN ADVANCED IDE Adapter EXM Menu Sub-Menu VME Menu Advanced Menu Exit Menu Memory Shadow Sub-Menu Boot Sequence Sub-Menu Keyboard Features Sub-Menu Figure 4-1. BIOS Setup Menu Map. Use the up and down cursor (arrow) keys to move from field to field. Use the right and left arrows to move between the menus shown in the menu bar at the top of the screen.

  • Page 37: Main Bios Setup Menu

    Chapter 4: BIOS Configuration Main BIOS Setup Menu The Main BIOS Setup Menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd. Main Advanced Exit Item Specific Help System Time: [16:17:18] System Date: [03/01/96] <Tab>, <Shift-Tab>, or Diskette A: [Not Installed] <Enter>...
  • Page 38 Use this field to select among the different video options available. Select from EGA/VGA, CGA 80x25, or monochrome. The default is “EGA/VGA”. The EPC-5A’s video is VGA, supplied by an EXM Video Module. Memory Shadow Sub-menu The term “Memory Shadow” refers to the technique of copying information from an extension ROM into DRAM and accessing it in this alternate memory location.

  • Page 39: Ide Adapter Sub-Menus

    There are a total of two IDE adapter sub-menus for the primary hard disk controller, in a master and slave drive configuration. The EPC-5A hard disk is controlled by the settings for IDE Adapter 0 Master. To see or reconfigure the detailed characteristics of the primary hard disk, select the IDE Adapter 0 Master item from the Main BIOS Setup.
  • Page 40 POST. Note that there are some restrictions when setting up devices on the EPC-5A. If you plan to boot from a non-IDE device, such as a SCSI hard disk, set the C: drive type as “None”...

  • Page 41: Memory Shadow Sub-Menu

    Chapter 4: BIOS Configuration Memory Shadow Sub-Menu The term “shadowing” refers to the technique of copying BIOS extensions from ROM into DRAM and accessing them from DRAM. This allows the CPU to access the BIOS extensions much more quickly and generally increases system performance if many calls to the BIOS extensions are made.

  • Page 42: Boot Options Sub-Menu

    EPC-5A Hardware & Software Reference Manual Boot Options Sub-menu Use the Boot Options sub-menu to change the boot sequence options. Select the Boot Options sub-menu by clicking on the Boot Sequence item in the Main BIOS Setup screen. The Boot Options Sub-menu is shown below.
  • Page 43 Chapter 4: BIOS Configuration 2. C: then A: Used to boot from the C: drive, or if none is present, boot from the A: drive. 3. C: only: Used to boot from the C: drive without searching for an A: drive.

  • Page 44: Keyboard Features Sub-Menu

    EPC-5A Hardware & Software Reference Manual Keyboard Features Sub-menu The Keyboard Features Sub-menu allows you to enable or disable various keyboard features. To access the keyboard Features menu, select Numlock in the Main BIOS Setup screen. The Keyboard Features Sub-menu is shown below.

  • Page 45: Advanced Menu

    Chapter 4: BIOS Configuration Keyboard auto-repeat delay Use this option to set the delay between when a key is pressed and when the auto- repeat feature begins. The options are “1/4 sec”, “1/2 sec”, “3/4 sec”, and “1 sec” . The default delay is “1/4 sec”.
  • Page 46 BIOS extensions. The screen graphic only shows the first group. Two extensions ship with the EPC-5A. The PicoFlash BIOS offset is 48000h, and the size is 2000h. The vRom BIOS offset is 4A000h, and the size is 4000h.

  • Page 47: Exm Menu

    Chapter 4: BIOS Configuration EXM Menu Use the options in this menu to select and configure the available EXM slots. The required configuration information is found in the hardware reference manual shipped with each EXM expansion module. The EXM Menu is shown below. PhoenixBIOS Setup - Copyright 1985-96 Phoenix Technologies Ltd.

  • Page 48: Figure 4-9. Slot Numbering

    EPC-5A Hardware & Software Reference Manual Option Byte 1 This option is used to select the first option byte value for the EXM card intended to reside in this slot. Option byte 1 typically defines bit 0 as the card enable bit. Other bits in the option byte are defined by the particular EXM card installed.
  • Page 49 Use DMA channels 1, 3, 6, and 7. Do not select I/O addresses that conflict with those in the EPC-5A. A complete list appears in Appendix A. For instance, I/O addresses in the 300-33F range can be used.

  • Page 50: Vme Menu

    This option is used to select among the four (0 through 3) VMEbus priority levels used when the EPC-5A requests the bus for a VME access. Priority level 0 is the lowest priority while priority level 3 is the highest priority. The default is priority level “0”.
  • Page 51 The default is “ROR (VME)”. Unique Logical Address This option is used to select the ULA for the EPC-5A. This logical address is used to uniquely identify and access the EPC-5A in a VXI system. The default is ULA “F8”.

  • Page 52: Exit Menu

    EPC-5A Hardware & Software Reference Manual Exit Menu The options in this menu allow saving settings and exiting, or abandoning changes and exiting to the system, or controlling the backup and restoration of CMOS RAM to the FBD. The Exit Menu is shown below.
  • Page 53 Chapter 4: BIOS Configuration The System BIOS software searches the FBD for the unterminated string “RadiSysCMOS--->” at power-up. This footprint marks the beginning of the CMOS parameter block storage structure. The structure contains a 16-bit CRC of the CMOS RAM data that is calculated at backup time and recalculated at restoration time. If the CRC verification fails, the restoration is skipped.
  • Page 54 EPC-5A Hardware & Software Reference Manual Load previous values This option is used to load the system with the previous values before an editing session started. Save Changes This option is used to save the edits made during a session.

  • Page 55: Theory Of Operation

    5. Theory of Operation The EPC-5A is a PC/AT compatible processor. Most of the standard functions of the PC architecture is embodied in the RadiSys R400 chip set. In addition, the EPC-5A has two proprietary interfaces: one for the EXM expansion interface and the other for the VMEbus.

  • Page 56: Memory

    Memory The following memory options are available: 4 MB, 8 MB, 16 MB, 32 MB and 64 MB. (Check with RadiSys Technical Support for 128 MB and 256 MB configurations.) Two SIMM sockets are available. See Chapter 8, Upgrades, for memory upgrade instructions.

  • Page 57: Memory Map

    DOS as upper memory blocks if an EMM driver is installed or may be used for BIOS extensions. For a 4 MB EPC-5A, the extended memory address space is defined as 00100000 003FFFFF 3 MB DRAM extended memory 00400000 00FEFFFF Uncommitted;...

  • Page 58: Peripheral Components

    EPC-5A Hardware & Software Reference Manual For a 32 MB EPC-5A, the extended memory address space is defined as 00100000 01FFFFFF 32764 KB DRAM extended memory For a 64 MB EPC-5A, the extended memory address space is defined as 00100000...

  • Page 59: Keyboard Controller

    64h. Keyboard interrupts are signaled on IRQ1. ROM and ROM Shadowing The EPC-5A contains a 28F004-B*-T Flash Boot Block. The Flash device is mapped into the top of the processor’s 32-bit address space. The Flash device contains the PC BIOS, some peripheral BIOS code, and user extensions.

  • Page 60: Battery

    60°C, the battery is estimated to have a life of 10 years. The battery supplied with the EPC-5A is mounted on the underside of the metal frame and connected to a header on the processor board. Should the battery fail, you may obtain and install a replacement from RadiSys Technical Support.

  • Page 61: Video Controllers

    RAM, or that directly call video BIOS functions will fail. Front Panel LEDs The EPC-5A has five LEDs in the top left corner of the front panel. These LEDs are described below: This LED is lit whenever the EPC-5A’s CPU is performing bus cycles.

  • Page 62: Resetting The Epc-5A

    Configuring the BIOS Setup, in the section on the EXM Setup Menu. The EXM expansion interface is provided on rows A, C, and D of the EPC-5A's 4-row DIN P2 connector. The subplane carries the EXM interface to other modules, such as to EXM modules and the EXP-MX Mass Storage module.

  • Page 63: The Vmebus Interface

    EPConnect software, an easy-to-use, high-level interface that frees you from most machine-dependent considerations. Connectivity The EPC-5A module connects to the VMEbus J1 connector directly and uses all of the defined VMEbus lines except SERCLK...

  • Page 64: Concepts

    EPC-5A asserts the VMEbus BERR signal until both data strobes are deasserted. The duration of the VMEbus timeout counter is 100-120 µsecs. When the EPC-5A is configured as the slot-1 controller, this timeout cannot be disabled and the duration cannot be changed.

  • Page 65: Direct Vmebus Accesses

    Chapter 6: The VMEbus Interface It should be noted that the EPC-5A drives all 32 address lines even when performing an A24 or A16 access. Therefore, all the above registers (8150, 8151, 8130) should be set for every access using the VME memory window. Make sure that those registers not directly supplying address lines are set to “FF”...

  • Page 66: Byte Ordering

    VME memory window mapping registers. When using the EPC-5A this way to perform VMEbus accesses, one would typically set up the VME memory window for interrupt acknowledge accesses. Also note that...

  • Page 67: Figure 6-3. Little-Endian Byte Order

    Byte 1 Byte 0 The EPC-5A contains programmable byte-swapping hardware to allow programs to read or write VMEbus memory in either byte order. When using the VME memory window to access the VMEbus, the order is selected by bit 5 (BORD) in the VME modifier register (8151).

  • Page 68: Figure 6-4. Big-Endian Byte-Swapping

    CAUTION Byte swapping applies only to EPC-5A initiated (master) accesses; it does not apply to slave accesses from other VMEbus masters to the EPC-5A’s DRAM. The EPConnect Bus Manager software provides a means of selecting the byte ordering during memory-copy operations.

  • Page 69: Slave Accesses From The Vmebus

    As such, care must be taken in writing to the EPC-5A’s memory. When such an access is fielded by the EPC-5A, the EPC-5A’s A24 or A32 base address is effectively subtracted from the VMEbus address value, and the result is treated as if the access came from the 486.

  • Page 70: Self Accesses Across The Vmebus

    When such a read occurs that is mapped to the VMEbus, the EPC-5A treats it as the start of a VME RMW cycle. The next VME access from the CPU is treated as the write that terminates the RMW cycle. Keep in mind that accesses that cross a 32-bit boundary are actually performed as two accesses.

  • Page 71: Vmebus Interrupt Response

    DRAM or the cache, VMEbus slave accesses are held up until the last locked access completes. One more case of interest is when the EPC-5A performs a locked access that results in a self access. These function correctly (i.e., as if the access was not a self access), providing that operating-system tables (e.g., page tables) that are accessed by the CPU...

  • Page 72: Registers Specific To The Epc-5A

    EPC-5A Hardware & Software Reference Manual Registers Specific to the EPC-5A Registers in the I/O space that are specific to the EPC-5A are defined below. I/O Port 8104h MEMSIZE VMEbus and Memory Controller Configuration 8130h VMEbus Address bits 21-16 VME A21-16 Address Register...
  • Page 73 Chapter 6: The VMEbus Interface Protocol Register, lower 8149h Protocol Register, upper 814Ah LOCK ABMH Response Register, lower 814Bh RRDY WRDY Response Register, upper 814Ch Message High Register, lower 814Dh Message High Register, upper 814Eh Message Low Register, lower 814Fh Message Low Register, upper 8150h VMEbus Address bits 31-24...
  • Page 74 (that is, when the RESET button is pushed or power is applied to the system). MEMSIZE Memory Size. These bits tell the memory controller how much SIMM DRAM memory is present on the EPC-5A. This field is set by the BIOS when power is applied to the EPC-5A, and contains one of the following values: 001 = 4 MB, 010 = 8 MB, 111 = 16 MB, 110 = 32 MB.
  • Page 75 VME A21-16 Address Register (8130h) VMEbus Address bits 21-16 When an access is performed by the EPC-5A in its window (address range 0E0000h- 0EFFFFh), the access is mapped onto the VMEbus. The least-significant 16 of the VME address bits are provided directly (from the 486), and the remaining 8 (for an A24 access) or 16 (for an A32 access) bits must come from somewhere else.
  • Page 76 6. If bit 6 is set, the value of the register is 7Fh and the A32 bit in the previous register is 1. This denotes that the EPC-5A responds to a 16 MB range in the A32 space.
  • Page 77 1.3 of the VXIbus specification. PASS If set (1), the EPC-5A has completed its self test successfully. If this bit is clear, the Test LED on the EPC-5A front panel is lit. NOSF SYSFAIL inhibit.
  • Page 78 18 - 1F, which correspond to the base addresses 18000000h - 1F000000h. If A32 is clear and SLE is set, the two low-order bits of SLAVE BASE define the base address of the EPC-5A’s memory in A24 as follows: 00 - 000000h, 01 - 400000h, 10 - 800000h, 11 - C00000h.
  • Page 79 VME A31-24 Address Register (8150h) VMEbus Address bits 31-24 (WA31-24) This register is one of several that supply the VMEbus address bits when the EPC-5A makes an access in its memory window. This register supplies VME address bits A31- A24.
  • Page 80 BORD IACK This register is also used when the EPC-5A makes an access through its VME memory window to the VMEbus. Bits 7 and 6 provide VME address bits A23 and A22, respectively. Bits 3-0 define the value placed on the associated VMEbus address-modifier lines.
  • Page 81 If any bit in this register is a 1 and the corresponding bit in the event state register is a 0, the EPC-5A IRQ10 interrupt is asserted. Software may then examine the interrupt and event state registers to determine the cause.
  • Page 82 This register is used to assert one of the VMEbus interrupt signals. If the INTERRUPT-OUT bits are zero, no interrupt line is asserted by the EPC-5A. If the lower three bits are set to 001, VMEbus IRQ1 is asserted. If set to 010, VMEbus IRQ2 is asserted, and so on.

  • Page 83: Vmebus Mapped Registers

    VMEbus A16 space and thus accessible by other VMEbus modules. These registers are 16-bit registers occupying 64 bytes of A16 space at a base address defined by the EPC-5A’s logical address. The base address is 1111 111a aa00 0000 where aaa is the value of the ULA field in the response register at I/O port 814A.

  • Page 84: Register State After Reset

    (immediately after the current value of the response register is returned). Register State after Reset A hardware reset of the EPC-5A (not a keyboard CTRL+ALT+DEL reset) clears all of the register bits to 0, except for RELM, ARBM, ARBPRI, and the registers at ports 8130h, 8150h, and 8151h, which may be in an undefined state.

  • Page 85: Low-Level Programming The Vmebus Interface

    Chapter 6: The VMEbus Interface Low-Level Programming the VMEbus Interface It is recommended that rather than performing accesses in this low-level hardware dependent form, the Bus Manager component of the EPConnect software package be used instead. VMEbus Accesses Two examples are given here including both a verbal description and the Microsoft C source code for performing VMEbus accesses through the memory window.
  • Page 86 EPC-5A Hardware & Software Reference Manual Bits 3-0 Use the address modifier (in binary form) to determine the appropriate values for these bits. 2Dh = 00101101b Bit 3 (Address Modifier bit 5) = 1 Bit 2 (Address Modifier bit 4) = 0...
  • Page 87 Chapter 6: The VMEbus Interface Example #2 performs a byte (8-bit) write into the VMEbus A32 space. Here the upper 16 bits of the VME address need to be stored in the appropriate registers. Set the VME access bit in register 8104h. Set register 8150h with the value corresponding to the 8 high-order address bits.

  • Page 88: Low-Level Handling Of Vmebus Interrupts

    The following is a description of how VMEbus interrupts (IRQ1-IRQ7), VXIbus message interrupts and error interrupts (BERR, ACFAIL, WDTG, etc.) should be handled on the EPC-5A. Note that, in general, the use of EPConnect is highly recommended to handling interrupts.
  • Page 89 Chapter 6: The VMEbus Interface • Keep in mind that while PC/AT interrupts are edge sensitive, VMEbus interrupts are level sensitive. As such, you must ensure that 1) The 8259 interrupt controller is enabled to capture interrupts before a VMEbus interrupt occurs (otherwise VMEbus interrupts will be totally missed) and 2) You must handle all pending VMEbus interrupts before returning from the interrupt handler.
  • Page 90 EPC-5A Hardware & Software Reference Manual Start of Loop • Determine the source of the interrupt or event. This can be done by reading the VME Interrupt State register which should be ANDed with the VME Interrupt Enable register. As described above, the VME Event State register and VME Event enable register may also be potential sources for the generation of IRQ10.
  • Page 91 Chapter 6: The VMEbus Interface • Upon returning from the interrupt handling routine, go back to the beginning of the loop until no more interrupts are active. In other words, you must handle all other active interrupts. This includes all other interrupts and errors which come in prior to calling the interrupt handling routine as well as any new interrupts and errors which may occur during this process.
  • Page 92 EPC-5A Hardware & Software Reference Manual NOTES Page 86...

  • Page 93: Connectors

    All but the battery and speaker headers are on the front panel. Pins are labeled from the point of view of looking into the front of the connector on the EPC-5A. Serial Ports The COM1 and COM2 serial ports are DB-9 DTE connectors defined in the following table.

  • Page 94: Parallel Port

    EPC-5A Hardware & Software Reference Manual Parallel Port The DB-25 LPT1 parallel port connector is an Output-Only device defined as: Pin Signal Pin Signal 1 Strobe 14 Auto line feed 2 DB0 15 Error 3 DB1 16 Initialize printer 4 DB2...

  • Page 95: Speaker Header

    Chapter 7: Connectors Speaker Header The speaker header is located on the EPC-5A circuit board and is defined as: Signal Signal Reference voltage Speaker tone Table 7-4. Speaker Header Pinout. Battery Header The battery header is located on the EPC-5A circuit board and is defined as:...
  • Page 96 EPC-5A Hardware & Software Reference Manual NOTES Page 90...

  • Page 97: Upgrades

    CAUTION Do not handle the EPC-5A module unless you are in a static-free environment. Memory The EPC-5A can be configured for various memory sizes. The 100 MHz EPC-5A memory configurations use SIMMs with the following specifications: • 72 pin •...

  • Page 98: Figure 8-1. Simm Memory Location

    EPC-5A Hardware & Software Reference Manual Figure 8-1. SIMM Memory Location. After upgrading the memory, power up the machine and press F2 to enter the Main BIOS Setup Menu. Verify that the top line of this screen shows the correct amount of memory.

  • Page 99: Troubleshooting & Error Messages

    If an error message is displayed, see the next section of this chapter, Common Error Messages. Always attempt to solve the problem yourself. If you are unable to solve the problem, call RadiSys Technical Support. Make sure you have detailed system configuration available before starting your phone call.
  • Page 100 EPC-5A Hardware & Software Reference Manual Symptoms Possible cause(s) Solution System fails at power-up - The system is not getting Check the backplane and verify that will not run power-on self- power. +5V power is good. Verify that the test.

  • Page 101: Common Error Messages

    Something in the nonvolatile CMOS RAM is incorrect. Solution(s): Run the BIOS setup program to determine what is wrong, and correct it. If the error occurs repeatedly, the EPC-5A's battery has failed. CMOS RAM ERROR, CHECK BATTERY / RUN SETUP Problem: Something in the nonvolatile CMOS RAM is incorrect.
  • Page 102 EPC-5A Hardware & Software Reference Manual DISK BOOT FAILURE, INSERT SYSTEM DISK AND PRESS ENTER Problem: No boot disk could be found. Solution(s): This could occur in several different ways. Your hard disk may not have been partitioned into logical drive(s).
  • Page 103 Solution(s): If you have no floppy diskette drives, enter the setup program and set both floppy drives to “NONE.” If you are using an EXP-MX module, verify that the EPC-5A, subplane, and EXP-MX are properly seated, and check the LEDs on the front panel of the EXP-MX to ensure that both the +5V and +12V supplies are available.
  • Page 104 EPC-5A Hardware & Software Reference Manual GENERAL FAILURE READING DRIVE ... Problem: This almost always indicates the presence of an unformatted hard disk partition or diskette. Solution(s): Format the partition or diskette using the utilities supplied by your operating system.
  • Page 105 Chapter 9: Troubleshooting & Error Messages MEMORY PARITY INTERRUPT AT ... Problem: This could be a software error (reading a nonexistent memory area) or a true hardware failure. Solution(s): Attempt to repeat the error. If the error occurs during the execution of your own proprietary software, verify that the memory location specified in your software is valid.
  • Page 106 Problem: The battery-backed TOD clock is incorrect. Solution(s): Run the BIOS setup program to determine what is wrong, and correct it. If the error occurs repeatedly, the EPC-5A’s battery has failed. TESTING VME (VXI) INTERFACE FAILED Problem: The BIOS Post has detected that the VME or VXI registers are invalid.
  • Page 107 Chapter 9: Troubleshooting & Error Messages Page 101...

  • Page 108: Boot Failures

    EPC-5A Hardware & Software Reference Manual Boot Failures The System BIOS attempts to display an error message on the display and halts when it encounters the following error conditions: Fixed disk error Causes : • No drive connected • Configured for 0 cylinders •...

  • Page 109: Phoenix™ Nubios Checkpoints

    Chapter 9: Troubleshooting & Error Messages Phoenix™ NuBIOS Checkpoints The Phoenix™ NuBIOS writes a number of checkpoints to I/O port 80h just before they are executed. Note that the execution order of the POST tests generally follows the order listed in the tables below, but not exactly. In addition, some checkpoints are not implemented, but the entire table is presented here for completeness.
  • Page 110 EPC-5A Hardware & Software Reference Manual Shadow system BIOS ROM Reinitialize the cache Autosize cache Configure advanced system controller registers Load alternate registers with CMOS values Set initial CPU speed Initialize interrupt vectors Initialize BIOS interrupts 2-1-2-3 Check ROM copyright notice...

  • Page 111: Table 9-1. Phoenix Nubios Checkpoint Codes

    Chapter 9: Troubleshooting & Error Messages Detect and install external RS232 ports Detect and install external parallel ports Initialize PNP ISA devices Re-initialize onboard I/O ports Initialize BIOS Data Area Initialize Extended BIOS Data Area Initialize floppy controller Initialize hard disk controller Initialize localbus hard disk controller Jump to UserPatch2 Build MPTABLE for multiprocessor boards...

  • Page 112: Table 9-2. Phoenix Nubios Auxiliary Checkpoint Codes

    EPC-5A Hardware & Software Reference Manual Beep Code Post Code Checkpoint Description Interrupt handler error Unknown interrupt error Pending interrupt error Initialize option ROM error Shutdown error Extended block move Shutdown 10 error Table 9-2. Phoenix™ NuBIOS Auxiliary Checkpoint Codes.

  • Page 113: 10. Support And Service

    Technical Support Services are designed for customers who have purchased their products from RadiSys or a sales representative. If your RadiSys product is part of a piece of OEM equipment, or was integrated by someone else as part of a system, support will be better provided by the OEM or system vendor that did the integration and understands the final product and environment.

  • Page 114: Repair Services

    EPC-5A Hardware & Software Reference Manual Repair Services Factory Repair Service is provided for all RadiSys products. Standard service for all RadiSys products covers factory repair with customers paying shipping to the factory and RadiSys paying for return shipment. Overnight return shipment is available at customer expense.

  • Page 115: Arranging Service

    There is a minimum billing charge associated with this program. Arranging Service To schedule service for a product, please call RadiSys RMA Dispatcher directly at (800) 256-5917. Have the product model and serial numbers available, along with a description of the problem. An RMA Dispatcher will issue a Returned Materials Authorization (RMA) number, a code number by which we track the product while it is being processed.

  • Page 116: Other Countries

    Any ancillary information that might be helpful with the debugging process will be appreciated. Other Countries Contact the sales organization from which you purchased your RadiSys product for service and support. Page 110...

  • Page 117: Appendix A: Chip Set & I/O Map

    Appendix A: Chip Set & I/O The following defines the I/O addresses decoded by the EPC-5A. It does not define addresses that might be decoded by EXMs and the EXP-MX. First (8-bit) DMA controller: R400 chip emulating 8237 of PC/AT...
  • Page 118 EPC-5A Hardware & Software Reference Manual Counter-Timer functions: R400 emulating 8254 of PC/AT I/O Addr Functional group Usage Timer Counter 0 Counter 1 Counter 2 Control (W) Keyboard Port: Intel 8242 emulating 8742 of PC/AT I/O Addr Functional group Usage...
  • Page 119 Appendix A: Chip Set & I/O Map Second Interrupt Controller: R400 emulating 8259 of PC/AT I/O Addr Functional group Usage Interrupt controller 2 Port 0 Port 1 Second (16-bit) DMA Controller: R400 emulating 8237 of PC/AT I/O Addr Functional group Usage Channel 4 address Channel 4 count...
  • Page 120 EPC-5A Hardware & Software Reference Manual Coprocessor Interface: On the EPC-5A, 486’s built-in coprocessor replaces the 80287 of PC/AT I/O Addr Functional group Usage Coprocessor Clear coprocessor busy Reset coprocessor Serial I/O (ComB) Port: TI 16C452 emulates PC/AT chipset I/O Addr...
  • Page 121 Appendix A: Chip Set & I/O Map EPC-5A Memory Mapping Registers: No PC/AT equivalent I/O Addr Functional group Usage 8130 VME and misc control VME map WA21-16 8132 Alias of 8130 8134 Alias of 8130 8136 Alias of 8130 8140...
  • Page 122 EPC-5A Hardware & Software Reference Manual NOTES Page A-6...

  • Page 123: Appendix B: Interrupts And Dma Channels

    Appendix B: Interrupts and DMA Channels Interrupts The assignment of interrupts for the EPC-5A is shown in the following table: DRAM parity error, EXM expansion interface I/O channel check IRQ0 timer IRQ1 keyboard IRQ2 IRQ8 - IRQ15 cascade through IRQ2...

  • Page 124: Dma Channels

    EPC-5A Hardware & Software Reference Manual DMA Channels The assignment of DMA channels for the EPC-5A is shown in the following table. 0 unassigned (8-bit) 1 unassigned (8-bit) 2 usually needed for floppy disk (8-bit) 3 usually needed for SCSI disk (8-bit)

  • Page 125: Appendix C: Flash Boot Device

    Appendix C: Flash Boot Device The system BIOS is based on the Phoenix™ NuBIOS version 4.05 implemented as a Flash BIOS using the Intel 28F004BV-T SmartVoltage Boot Block Flash Device (hereafter referred to as the Flash Boot Device or FBD). System BIOS code and data reside in the 16KB boot block, parameter block #1, parameter block #2 (CMOS data), and the 96KB main block (#4).

  • Page 126: Figure C-1. Flash Boot Device Memory Map

    EPC-5A Hardware & Software Reference Manual The Flash Boot Device is organized according to the following diagram: Physical Address 28F004BV-T Device Offset (Real Mode Address) FFFFFFFFh (FFFFFh) 7FFFFh 16KB Boot Block FFFFC000h (FC000h) BIOS Recovery code 7C000h FFFFBFFFh (FBFFFh) 7BFFFh...

  • Page 127: Flash Boot Device Reflashing

    Table C-1. FBD Object Placement. Flash Boot Device Reflashing The EPC-5A System BIOS is updated by using a special boot diskette that contains code to perform the update as well as the System BIOS image itself. The floppy update mechanism is standard to the Phoenix NuBIOS and requires that a standard PC floppy diskette drive be installed in the system.
  • Page 128 MS-DOS. The Phoenix update program, PHLASH.EXE, may be executed on the EPC-5A after it has booted to MS-DOS. The user may initiate the update by changing to the drive containing the PHLASH.EXE and executing it on the EPC-5A. Note that the PHLASH.EXE program can only be executed from MS-DOS (and without MS-...

  • Page 129: Figure C-2. Flash Boot Device Recovery Mechanism

    Appendix C: Flash Boot Device The update process is outlined in the following flow chart: start Force jumper installed? CMOS Reflash byte Turn off CMOS Reflash Do floppy Checksum recovery Load Reboot Figure C-2. Flash Boot Device Recovery Mechanism. Page C-5...

  • Page 130: Reflashing Using Reflash.exe

    Reflashing using REFLASH.EXE The FBD can also be reprogrammed using the RadiSys MS-DOS™ utility REFLASH.EXE. This is a flash read/modify/write utility that is useful for reprogramming the entire FBD or programming a single BIOS extension into the FBD while leaving the rest of it intact.
  • Page 131 Physical base address of the region to be flashed. This parameter does not apply to the EPC-5A. If this switch is omitted, the FBD is the default reflash target. To update the FBD, follow the instructions below: Run: Reflash /F=[update_file_name] /O=0 to begin the update.

  • Page 132: User Bios Extensions

    EPC-5A Hardware & Software Reference Manual User BIOS Extensions The EPC-5A supports several different boot methods and OSes. In order to boot from VME or flash, it is necessary to first load and execute a BIOS extension. The FBD has an unused 96KB region in main block #3 that lies between the end of the PicoFlash extension and start of the System BIOS that can be used for BIOS extension storage.

  • Page 133: Picocard Flash File System

    Appendix C: Flash Boot Device PicoCard Flash File System The EPC-5A contains a BIOS used to access the Flash as a read/write disk. If the user selects shadowing of the PicoCard memory region, the extension is loaded to initialize the disk.
  • Page 134 EPC-5A Hardware & Software Reference Manual NOTES Page C-10...

  • Page 135: Appendix D: Pformat

    Appendix D - PFormat The EPC-5A supports use of EXM-2A flash cards as Chapter 2 discusses. The supported configurations require the use of appropriate software to provide drivers and a suitable format. This appendix briefly describes the software from RadiSys.
  • Page 136 EPC-5A Hardware & Software Reference Manual Step 1B (Load as BIOS extension) Note that if the driver is loaded as a BIOS extension, the system will attempt to boot from the device. This means that the RFA must be formatted and loaded with system files before the driver can be successfully loaded as a BIOS extension.
  • Page 137 PFormat Step 2: Format the drive Assuming that the driver loaded successfully (either as a device driver or as a BIOS extension), run the PFORMAT.EXE utility as follows: PFORMAT D: /C /V The /C confirms the format, and the /V switch says to put a volume label on the drive.
  • Page 138 EPC-5A Hardware & Software Reference Manual NOTES Page D-4...

  • Page 139: Appendix G: Glossary

    Appendix G: Glossary  A  Access Time: A factor in measurement of a memory storage device’s operating speed. It is the amount of time required to perform a read operation. More specifically, it is the period of time between which the memory receives a read command signal and the time when the requested data becomes available to the system data bus.
  • Page 140 EPC-5A Hardware Reference  B  Basic Input/Output System (BIOS): Firmware in a PC-compatible computer that runs when the computer is powered up. The BIOS initializes the computer hardware, allows the user to configure the hardware, boots the operating system, and provides standard mechanisms that the operating system can use to access the PC’s peripheral devices.
  • Page 141 Glossary Boot Sequence: The order in which a computer searches external storage devices for an operating system to boot. The boot device must be the first in the boot sequence. Byte: A group of 8 bits.  C  Central Processing Unit (CPU): A semiconductor device which performs the processing of data in a computer.
  • Page 142 EPC-5A Hardware Reference CMOS Save and Restore (CSR): A System BIOS feature that allows the user to backup the contents of CMOS RAM (contained within the real time clock) to the BIOS Flash device to be restored later if necessary (such as when the real time clock battery dies).
  • Page 143 Flash Boot Device (FBD): A flash memory device containing the computer’s BIOS. In the EPC-5A, a 512 KB Intel 28F004BV-T semiconductor flash memory containing the system and video BIOS images, the BIOS initializing code and the recovery code which allows self hosted reflashing.
  • Page 144 EPC-5A Hardware Reference  G  Gigabyte (GB or GByte): Approximately one billion (US) or one thousand million (Great Britain) bytes. 2 = 1,073,741,824 bytes exactly.  H  Hang: A condition where the system microprocessor suspends processing operations due to an anomaly in the data or an illegal instruction.
  • Page 145 Glossary Interrupt Request (IRQ): In ISAbus systems, a microprocessor input from the control bus used by I/O devices to interrupt execution of the current program and cause the microprocessor to jump to a special program called the interrupt service routine. The microprocessor executes this special program, which normally involves servicing the interrupting device.
  • Page 146 EPC-5A Hardware Reference Memory: A designated system area to which data can be stored and from which data can be retrieved. A typical computer system has more than one memory area. See Conventional Memory and Extended Memory.  O ...
  • Page 147 Glossary Pinout: A diagram or table describing the location and function of pins on an electrical connector. Plastic Quad Flat Pack (PQFP): A popular package design for integrated circuits of high complexity. Power On Self Test (POST): A diagnostic routine which a computer runs at power up.
  • Page 148 EPC-5A Hardware Reference Real Time Clock (RTC): Peripheral circuitry on a computer motherboard which provides a nonvolatile time-of-day clock, an alarm, calendar, programmable interrupt, square wave generator, and a small amount of SRAM. In the EPC- 30, the RTC operates independently of the system PLL which generates the internal system clocks.
  • Page 149 Glossary Serial Port: A physical connection with a computer for the purpose of serial data exchange with a peripheral device. The port requires an I/O address, a dedicated IRQ line, and a name to identify the physical connection and establish serial communication between the computer and a connected hardware device.
  • Page 150 USB ports, all with identical connectors but capable of much higher throughput, upwards of 12Mbs. User Editable Drive (UED): A feature of the EPC-5A’s Phoenix NuBIOS. When a “User” type hard disk drive setting shows in the IDE Adapter Sub-Menu the BIOS queries the hard disk drive for the purpose of retrieving disk geometry.
  • Page 151 Index BIOS Data Area, G-2 BIOS extension term defined, G-2 BIOS Recovery term defined, G-2 BIOS setup, 54 A16, 3, 58, 59, 60, 72, 77, 78, 79 BIOS Update A24, 3, 58, 59, 60, 63, 69, 70, 72, 78 term defined, G-2 A32, 3, 58, 59, 60, 63, 69, 70, 72, 78, block transfers, 63 Boot Block...
  • Page 152 EPC-5A Hardware & Software Reference Manual chassis, 13 Chipset EDO DRAMs term defined, G-3 term defined, G-5 CMOS RAM, 27, 52 electrical specs, 4 CMOS Setup, 97 electrostatic discharge, 7 CMOS setup parameters, 52 EMM driver, 49 COM1, 3, 26, 87...
  • Page 153 Index interrupt generator register, 65 interrupt mapping, B-1 Fast Page Mode DRAMs Interrupt Request (IRQ) term defined, G-5 term defined, G-7 Flash Boot Device interrupts, 83 term defined, G-5 IRQ10 interrupt, 75 Flash memory, 3 Flash Recovery term defined, G-5 Flash Update J1 connector, 12, 57 term defined, G-5...
  • Page 154 EPC-5A Hardware & Software Reference Manual MEMORY PARITY INTERRUPT, term defined, G-9 power-on self-test, 54 memory upgrades, 48, 91 printer port, 26, 41 message high register, 73 priority, 57 message interrupt, 74 priority arbiter, 71 message protocol, 73 Priority levels, 30...
  • Page 155 Index servant, 72 troubleshooting, 93 service, 107 setup parameters, 52 setup screen, 25, 53 unique logical address, 65, 72, 77 shadowing, 51 upgrades, 91 SIMMs, 48, 91 User Editable Drive (UED) Single In-Line Memory Module term defined, G-12 (SIMM) term defined, G-11 slave, 53, 63, 65 slave accesses, 64 slave base, 72...
  • Page 156 EPC-5A Hardware & Software Reference Manual NOTES Page I-VI...

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