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RadiSys EPS-6315 Hardware Reference Manual

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EPC
-6315 Hardware
Reference
www.radisys.com
007-01361-0005 • April 2005

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Summary of Contents for RadiSys EPS-6315

  • Page 1 ® -6315 Hardware Reference www.radisys.com 007-01361-0005 • April 2005...
  • Page 2 Copyright ©2005 by RadiSys Corporation. All rights reserved. EPC and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ, MultiPro, MultiPro, Promentum, SAIB, Spirit, and ValuePro are trademarks of RadiSys Corporation. DAVID, MAUI, OS-9, OS-9000, and SoftStax are registered trademarks of RadiSys Microware Communications Software Division, Inc.
  • Page 3 Before you begin This guide describes EPC-6315, a PrPMC (Processor PCI Mezzanine Card) that uses † the RadiSys 82600 integrated chipset to bring an Intel Architecture processor into ultra-dense form factors. This guide is for hardware and software designers, engineers, and those with a electronics and/or programming knowledge who need to understand the EPC-6315 operation.
  • Page 4 Readme file: Lists features and issues that arose too late to include in other documentation. • World Wide Web: RadiSys maintains an active site on the World Wide Web. The RadiSys web site site contains current information about the company and locations of sales offices, new and existing products, contacts for sales, service, and technical support information.

  • Page 5: For Mv Linux Lsps, Contact Montavista At This Url

    Before you begin To access the RadiSys web site, enter this URL in your web browser: http://www.radisys.com Requests for sales, service, and technical support information receive prompt response. • Other: If you purchased your RadiSys product from a third-party vendor, you can contact that vendor for service and support.
  • Page 6 ® -6315 Hardware Reference...

  • Page 7: Table Of Contents

    Before you begin About this guide ..........................Contents............................. Notational conventions ......................Where to get more information......................About EPC-6315........................About related RadiSys products ....................About related EPC-6315 components ..................Other ............................Chapter 1: Introduction Features ............................Compatibility........................Intel Tualatin LP processors in micro-FCBGA package............
  • Page 8 Organization............................. 52 Block diagram ..........................52 Intel Tualatin-LP 512K processor ..................... 52 Speed and voltages ........................53 Clocking ............................53 RadiSys 82600 system controller ...................... 54 Power-up configuration......................55 Host bridge.......................... 56 Memory subsystem ......................56 Memory map ........................56 BIOS flash support.......................

  • Page 9: Contents

    PCI ............................85 Jn1 ............................. 86 Clocking ..........................86 Arbitration........................... 86 Jn2 ............................. 86 Processor PMC ........................86 RadiSys-defined PrPMC connector (Jn4) ..................86 IDE ............................86 Keyboard and mouse........................86 Serial port ..........................87 Clocking............................. 87 Arbitration ..........................87 RTC battery ..........................
  • Page 10 ® -6315 Hardware Reference Figures Figure 1-1. The EPC-6315........................Figure 2-1. Installing a PMC module....................... Figure 2-2. Separating a PMC module from the carrier card ..............10 Figure 4-1. BIOS Main Setup menu......................25 Figure 4-2. Primary Master/Slave sub-menus................... 27 Figure 4-3.

  • Page 11: Chapter 1: Introduction

    133MHz PSB and 133MHz memory bus. For maximum flexibility, the EPC-6315 leverages the dual mode PCI-to-PCI bridge capability of the RadiSys 82600 to automatically configure the bridge based on the strapping of the slot on the baseboard. This capability allows the EPC-6315 to...

  • Page 12: Features

    Switching power supply for CPU core voltage; linear supplies for interface voltages. CPU subsystem • RadiSys 82600 dual PCI embedded system controller: For detailed information about the 82600 chip, see the 82600 High Integration Dual PCI System Controller Data Book.

  • Page 13: Specifications

    Chapter 1: Introduction • On-board memory capacity: up to 512 Mbytes of PC-133 compliant SDRAM. • 32 Mb (4 MB) 3V Intel Strata Flash memory. • Intel PCI Ethernet controller independently supporting 10BASE-T or 100BASE-TX. • Compact Flash. Connectors • Carrier card •...

  • Page 14: Table 1-1. Environmental Specifications

    ® -6315 Hardware Reference Table 1-1. Environmental specifications Parameter Conditions Detailed specification Temperature Operating +5ºC to 50ºC derated 2ºC per 1000 ft (300 m) over (ambient) 6600ft (2000m) with 200 LFM airflow. Storage –20ºC to +60ºC. Relative humidity Operating 20% to 90% non-condensing 20% per hour maximum excursion gradient..

  • Page 15: Additional Specifications

    Chapter 1: Introduction Additional specifications Table 1-2. Additional EPC-6315 specifications Characteristic Value 74.0 mm x 149.00 mm Mechanical Dimensions Height, component side First 31mm 9.5mm Remainder 4.7mm, maximum 3.5mm (this includes the 1.6mm board Height, solder side thickness) Thickness 1.6 mm Component surface to 10 mm host component surface...
  • Page 16 ® -6315 Hardware Reference...

  • Page 17: Chapter 2: Configuration And Installation

    Configuration and installation Chapter 2 This chapter describes how to install an EPC-6315 PMC on a RadiSys EPC board. For information about... Go to this page... Before you begin..................... 8 Installing the EPC-6315 PMC on the carrier card ............ 8 Maintaining and upgrading the EPC-6315 ............

  • Page 18: Before You Begin

    ® -6315 Hardware Reference Before you begin The EPC-6315 requires a PMC carrier. Installing the EPC-6315 PMC on the carrier card You install the EPC-6315 PMC on the carrier card as shown below. Figure 2-1. Installing a PMC module To install a PMC module: 1.

  • Page 19: Using The 3-Pin Connector

    COM1 signals. Before you begin, ensure that you have a null-modem cable that connects the 3-pin connector to your terminal. You must construct this cable; RadiSys does not supply a cable for the 3-pin connector. For pinout information, see 3-pin connector on page 76.

  • Page 20: Maintaining And Upgrading The Epc-6315

    ® -6315 Hardware Reference Maintaining and upgrading the EPC-6315 Occasionally you will want to perform maintenance or upgrades on the EPC-6315. When this occurs, you must remove the board from the carrier card, repair or install the desired option, then re-install the board on the carrier card. The following section describes how.

  • Page 21: Installing Red Hat Linux

    This document explains how to install Linux and VxWorks operating Ssstems on the EPC-6315. • For MV Linux LSPs, contact MontaVista at this URL: http://www.mvista.com • For VxWorks BSPs, contact RadiSys or WindRiver http://www.windriver.com http://www.radisys.com For information about... Go to this page...

  • Page 22: Installing Red Hat 7.3 Or Later Over The Serial Port

    ® -6315 Hardware Reference 4. Configure Linux for serial redirection. Using any editor, change these files: File Instructions /etc/inittab 1. Change the first TTY configuration line to read: 1: 2345:respawn:/sbin/mingetty ttyS0 115200 vt100 2. Comment out the remaining TTY configuration lines. 3.
  • Page 23 Chapter 3: Operating System Installation C. Change the console and terminal baud rates to 9600. D. Press F10 to save your changes, then reboot. The system boots over the serial port at 9600 bps, then displays the prompt. boot: Enter this command: linux console=ttyS0,9600n8 The serial port displays kernel messages.

  • Page 24: Installing Montavista Linux

    LSP, choose any LSP based on an Intel Pentium III processor. 3. Extract kernel source files from the RadiSys-supplied LSP archive to a work area. Configure DHCP Ensure that the DHCP server is configured correctly. An incorrect configuration may cause problems for other machines on your network.

  • Page 25: Configure Tftp

    Chapter 3: Operating System Installation B. Change the value of these parameters: The subnet address, consisting of four numbers from 0–255 SubAddress separated by dots (periods). The netmask address, consisting of four numbers from 0–255 NetAddress separated by dots (periods). The TFTP server address, consisting of four numbers from TFTPAddress 0–255 separated by dots (periods).

  • Page 26: Red Hat 7.X

    ® -6315 Hardware Reference Red Hat 7.x To configure TFTP on a Red Hat 7.x host as root: 1. Create (or edit) the file /etc/xinetd.d/tftp. Use the following format: #/etc/xinetd.d/tftp service tftp socket_type = dgram wait = yes user = root log_on_success += USERID log_on_failure += USERID server = /opt/mvlcge/host/bin/in.tftpd...

  • Page 27: Install Montavista Linux To A Hard Drive

    Chapter 3: Operating System Installation 3. Apply network boot headers to the kernel image by copying bzImage to /tftpboot. 4. Change the boot device: A. Attach: • An Ethernet cable to the EPC-6315 that allows access to your DHCP server. •...
  • Page 28 ® -6315 Hardware Reference For more information about fdisk, see the HOWTOs on using fdisk, available on the web. You can find out more about fdisk at www.redhat.com. To locate the utility, search for fdisk on the site. 2. Prepare a filesystem: A.

  • Page 29: Installing Vxworks

    Requirements To install a VxWorks BSP on an EPC-6315 you will need: • The EPC-6315 VxWorks BSP from RadiSys. You can request it from RadiSys by sending email to support@radisys.com. • A DOS boot disk with fdisk and format utilities.

  • Page 30: Installation

    ® -6315 Hardware Reference Installation 1. Install the BSP: A. Obtain the RadiSys EPC-6315 VxWorks BSP from RadiSys. You can request it from support@radisys.com. B. Install the BSP by extracting the archive and running setup.exe. 2. Build projects: A. In the Tornado environment, create a project based on the EPC6315 BSP.
  • Page 31 Chapter 3: Operating System Installation 5. Make a VxWorks-bootable hard drive or CompactFlash by entering these commands: Command Description vxsys c: Installs the master boot record and initial bootloader copy bootrom.sys c: Copies the VxWorks bootloader to the drive. copy vxWorks.st c: Copies VxWorks image to the drive.
  • Page 32 ® -6315 Hardware Reference...

  • Page 33: Chapter 4: Bios Configuration

    BIOS configuration Chapter 4 The EPC-6315 uses the Phoenix NuBIOS to configure and select various system options. This chapter details the various menus and sub-menus used to configure the system. This chapter is written as though you are setting up each field in sequence and for the first time.

  • Page 34: Menu Map

    ® -6315 Hardware Reference Menu map You set up the BIOS by making selections from the menus shown in the next table. When reading this file online, you can immediately view information about any menu by placing the mouse cursor over menu name and clicking: Menu Sub-menu Main Setup menu...

  • Page 35: Main Setup Menu

    Chapter 4: BIOS configuration Main Setup menu Figure 4-1. BIOS Main Setup menu PhoenixBIOS Setup Utility Main Main Advanced Boot Exit System Time: [16:17:18] Item Specific Help System Date: [01/01/2002] <Tab>, <Shift-Tab>, or <Enter> selects field. Primary Master [None] Primary Slave [None] System Memory: 640 KB...
  • Page 36 ® -6315 Hardware Reference Field Description Boot Options sub-menu Displays a menu that you use to specify the PC’s behavior during the boot process. For more information, see Boot menu on page 46. System memory Displays the amount of conventional memory (below 1MB). This field is not editable;...

  • Page 37: Primary Master/Slave Sub-Menus

    Chapter 4: BIOS configuration Primary Master/Slave sub-menus There are two IDE adapter sub-menus for the primary hard disk controllers: a master and slave drive menu. Access this screen to: • See or reconfigure the detailed characteristics of the primary hard disk (select the IDE Adapter 0 Master item from the Main BIOS Setup).
  • Page 38 • 1–39: Select this option to specify a pre-determined hard-disk drive type. These drive types, found in the FDPT (Fixed Disk Parameter Table), are seldom used. RadiSys recommends that you avoid using this option. Note: For disks not supplied, consult the product documentation.
  • Page 39 Chapter 4: BIOS configuration Field Description Multi-Sector Transfers Allows the System BIOS to read ahead by the specified number of sectors during disk access. This has the effect of reading more data at once to reduce the absolute number of discrete disk reads performed by the operating system, which may increase system performance.
  • Page 40 ® -6315 Hardware Reference Field Description Transfer Mode Selects the mode that the System BIOS uses to access the hard disk. You can select one of these: • Standard • Fast PIO 4 (default) • Fast PIO 1 • FPIO 3 / DMA 1 •...

  • Page 41: Advanced Menu

    Chapter 4: BIOS configuration Advanced menu This menu contains settings for integrated peripherals, memory shadow, cache, and large disk access mode. You access this menu by selecting Advanced from the Main BIOS Setup menu. Figure 4-3. Advanced menu PhoenixBIOS Setup Utility Main Main Advanced...
  • Page 42 ® -6315 Hardware Reference Field Description Reset Configuration Data Determines whether to clear the Extended System Configuration Data (ESCD) block that resides in the Flash Boot Device (FBD). You can select one of these: • No (default): Does not clear the ESCD block. •...

  • Page 43: Pci Configuration Sub-Menu

    Chapter 4: BIOS configuration PCI Configuration sub-menu Use the options in this sub-menu to control the exclusion of the UMB region for PCI or ISA and the exclusion of the IRQs for PCI or ISA. Figure 4-4. PCI Configuration sub-menu PhoenixBIOS Setup Utility Main Advanced...

  • Page 44: Prpmc Customizations Sub-Menu

    ® -6315 Hardware Reference PrPMC customizations sub-menu Options in this menu customize PrPMC options. Figure 4-5. PrPMC customizations sub-menu PhoenixBIOS Setup Utility Main Advanced PrPMC Customization Item Specific Help Backplane I/O [Disabled] <Tab>, <Shift-Tab>, or Backplane Ready [Enabled] <Enter> selects field. Memory Remap 0 [Use system BIOS Settings] Memory Remap 1...
  • Page 45 Chapter 4: BIOS configuration Field Description Memory Base/Limit n Forces memory/base and limit registers. You can select one of these: • Use system BIOS settings (default) • F100F000 • F900F800 • F300F200 • FB00FA00 • F500F400 • F000A000 • F700F600 SCSI Controller Determines the state of the SCSI controller on the carrier card.

  • Page 46: Pci/Pnp Isa Umb Region Exclusion Sub-Menu

    ® -6315 Hardware Reference PCI/PNP ISA UMB Region Exclusion sub-menu The PCI/PNP ISA UMB Region Exclusion Sub-Menu controls the exclusion of PCI and ISA UMB regions. Figure 4-6. PCI/PNP ISA UMB Region Exclusion sub-menu PhoenixBIOS Setup Utility Main Advanced PCI/PNP ISA UMB Region Exclusion Item Specific Help C800 –...

  • Page 47: Pci/Pnp Isa Irq Resource Exclusion Sub-Menu

    Chapter 4: BIOS configuration PCI/PNP ISA IRQ Resource Exclusion sub-menu The PCI/PNP ISA IRQ Resource Exclusion Sub-Menu controls the exclusion of PCI and ISA interrupt regions. Figure 4-7. PCI/PNP ISA IRQ Resource Exclusion sub-menu PhoenixBIOS Setup Utility Main Advanced PCI/PNP ISA IRQ Resource Exclusion Item Specific Help IRQ 3: [Available]...

  • Page 48: Cache Memory Sub-Menu

    ® -6315 Hardware Reference Cache Memory sub-menu The options in this sub-menu control the cacheability of certain memory regions and also the settings of the Level 2 (L2) cache. Figure 4-8. Cache Memory sub-menu PhoenixBIOS Setup Utility Main Advanced Memory Cache Item Specific Help Memory Cache: [Enabled]...
  • Page 49 Chapter 4: BIOS configuration Field Description Cache Base 0–512k Determines how the system caches base memory in the Cache Base 512–640k specified area: You can select one of these: • Write Back (default): Writes and reads to and from system memory are cached, then written to system memory when you perform a write-back operation.
  • Page 50 ® -6315 Hardware Reference Field Description Cache Memory Regions: Determines how the system deals with specified memory blocks or shadow memory. You can select one of these: A000–AFFF B000–BFFF • Disabled (default): The system does not cache memory. • USWC Caching: System memory locations are not cached (as with uncacheable memory) and coherency is not enforced by the processor’s bus coherency protocol.
  • Page 51 Chapter 4: BIOS configuration Field Description Cache Memory Regions: Memory regions. C800–CBFF Determines how the system deals with specified memory CC00–CFFF blocks or shadow memory. You can select one of these: D000–D3FF • Disabled (default): The system does not cache memory. D400–D7FF •...
  • Page 52 ® -6315 Hardware Reference Field Description Cache Memory Regions: Memory used in the E0000h–EFFFFh DRAM region. E000–E3FF Determines how the system deals with specified memory E400–E7FF blocks or shadow memory. You can select one of these: E800–EBFF • Disabled (default): The system does not cache memory. EC00–EFFF •...

  • Page 53: Console Redirection Sub-Menu

    Chapter 4: BIOS configuration Console Redirection sub-menu Options in this menu configure console redirection. Figure 4-9. Console Redirection sub-menu PhoenixBIOS Setup Utility Main Advanced Console Redirection Item Specific Help Com Port Address [On-board COM <Tab>, <Shift-Tab>, or <Enter> selects field. Baud Rate [115.2K] Console Type...
  • Page 54 ® -6315 Hardware Reference Field Description Console connection Specifies how the console connects to the system. You can select one of these: • Direct (default): Connects the console directly to the system. • Via modem: Connects the console to the system via a modem.

  • Page 55: I/O Device Configuration Sub-Menu

    Chapter 4: BIOS configuration I/O Device Configuration sub-menu Use the options in this sub-menu to configure the onboard serial disk controller. Figure 4-10. I/O Device Configuration sub-menu PhoenixBIOS Setup Utility Main Advanced I/O Device Configuration Item Specific Help Serial port A: [Auto] <Tab>, <Shift-Tab>, or <Enter>...

  • Page 56: Boot Menu

    ® -6315 Hardware Reference Boot menu The Boot menu: • Specifies the order in which the system tries to boot from devices attached to the system. • Specifies the boot order of devices in the same class, such as hard drives. Boot order is assigned from top to bottom, with the uppermost enabled boot device in each class being the boot candidate from that device class.
  • Page 57 Chapter 4: BIOS configuration To enable a device, highlight the desired device and press the Shift and 1 keys. An exclamation point ( ! ) displays to the left of enabled devices. To disable a device. highlight the device, then press the Shift and 1 keys again. Field Description Boot order...

  • Page 58: Exit Menu

    ® -6315 Hardware Reference Exit menu Use the options in this menu to save and exit, or abandon your changes and exit to the system. Figure 4-12. Exit menu PhoenixBIOS Setup Utility Main Main Advanced Boot Exit Exit Saving Changes Item Specific Help Exit Discarding Changes <Tab>, <Shift-Tab>, or <Enter>...

  • Page 59: Cmos Save & Restore Sub-Menu

    Chapter 4: BIOS configuration CMOS Save & Restore sub-menu Use the options in this menu to save, restore, or erase CMOS settings in the FBD (Flash Boot Device). Figure 4-13. CMOS Save & Restore sub-menu PhoenixBIOS Setup Utility Main Exit CMOS Save &...
  • Page 60 ® -6315 Hardware Reference...
  • Page 61 The RadiSys 82600 chipset provides the memory, PCI, IDE, and serial port interfaces. The Intel 82559 PCI controller provides on-board Ethernet.The EPC-6315 complies with the Processor PMC standard VITA 32-199X, Draft 0.41. Along with any configuration files and other information provided by RadiSys, the † † †...

  • Page 62: Organization

    Figure 5-1. EPC-6315: block diagram Intel Tualatin-LP Switching 512K processor power supply CPU clock Vcore Vtt PCI clock Memory clocks Backplane PCI RadiSys 82600 Front PCI clock and system controller panel arbitration Crystal Keyboard, mouse PCI Ethernet arbitration controller Local PCI...

  • Page 63: Speed And Voltages

    The processor’s 64-bit wide Assisted Gunning Transceiver Logic (AGTL) system bus provides a glueless, point-to-point interface for the RadiSys 82600 chipset. The Intel Tualatin 512K LP processor runs at a fixed 800 MHz internal speed with 133 MHz Processor Side Bus (PSB).

  • Page 64: Radisys 82600 System Controller

    ® -6315 Hardware Reference RadiSys 82600 system controller The 82600 is a highly integrated chipset. In an embedded Intel Architecture I/O system, the 82600 replaces four components: North Bridge, South Bridge, PCI-to-PCI Bridge and Super I/O. The chip includes: •...

  • Page 65: Power-Up Configuration

    Chapter 5: Theory of operation • Integrated Watchdog Timer: Detects system lockup. Flexible hardware reset or interrupt on timeout. • General Purpose Digital I/O: Multiplexed with other pin functions. 576 pin BGA package. The 82600 does not support the LOCK function on the local PCI or the BPCI buses.

  • Page 66: Host Bridge

    ® -6315 Hardware Reference Host bridge The 82600 connects directly to the AGTL CPU local bus. The processor die includes termination resistors. The 82600 segregates bus transactions as follows: • 36 address-bit references • SDRAM references • LPCI bus cycles •...

  • Page 67: Bios Flash Support

    Chapter 5: Theory of operation BIOS flash support BIOS ROM The re-programmable, 4Mbyte FBD (Flash BIOS Device) consists of 32 128KB blocks. The top 1 Mbyte holds the BIOS while the remainder is available for OEM non-volatile storage. For a map of the flash chip, see Appendix E, Flash memory addresses.

  • Page 68: Dual Pci Bus Architecture

    ® -6315 Hardware Reference Dual PCI bus architecture The 82600 integrates dual PCI busses, a local and backplane PCI bus. The LPCI (local PCI) bus can operate asynchronously at up-to the host processor’s clock rate or down-to one quater of this clock rate. Architecturally, it can be viewed as the high speed private peripheral bus for the processor.

  • Page 69: Local Pci Bus

    The EPC-6315 implements a +3.3V, 32 bit local PCI bus. The bus runs at 33 MHz and has the RadiSys 82600 chipset as the central resource. This PCI bus has one peripheral device connected to it, the Intel 82559 Ethernet controller.

  • Page 70: Ide Controller Flash Disk

    IDE cable set. For detailed information, see Appendix G, Carrier card design. The RadiSys 82600 provides an internal Real Time Clock (RTC) and 256 byte CMOS RAM functions. These perform the following functions: • Tracks time of day.

  • Page 71: Power

    Chapter 5: Theory of operation Power The next table represents the estimated EPC-6315 power consumption. This table includes the power requirements for the dual-die, +3.3V, nine SDRAM ICs. Table 5-4. Power estimates Watts Maximum Product configuration Voltage Typical EPC6315-800-512 +3.3V 6.0W 4.8W (800Mhz CPU, 133Mhz PSB, 512MB)

  • Page 72: Avoiding Memory Address And Data Misalignment

    As a workaround, you can set host bus I/O queue depth to 1 (instead of 8). This approach requires the addition of 1 each pull-up resistor on memory address 8. For detailed information, see these RadiSys 82600 documents, available on the RadiSys web site: •...

  • Page 73: Appendix A: Message Codes

    Message codes Appendix A This appendix lists the Phoenix BIOS 4.06 standard POST error codes which can generate console messages. Class Number Name 200h ERR_DISK_FAILED Disk errors 210h ERR_KBD_STUCK Keyboard errors 211h ERR_KBD_FAILED 212h ERR_KBD_KCFAIL 213h ERR_KBD_LOCKED 220h ERR_VIDEO_SWITCH Video errors 230h ERR_SYS_MEM_FAIL Memory errors...
  • Page 74 ® -6315 Hardware Reference Class Number Name 2D1h ERR_L2_CACHE_RANGE System memory exceeds CPU caching limit 2E0h ERR_IO_ADDRESS IO errors 2E1h ERR_IO_COM 2E2h ERR_IO_LPT 2E3h ERR_IO_CONFLICT 2E4h ERR_IO_UNSUPPORTED 2E5h ERR_IO_IRQ 2E6h ERR_IO_IDE 2E7h ERR_IO_FDD 2F0h ERR_OTHER_CPUID 2F1h ERR_OTHER_BIST 2F2h ERR_OTHER_BSP 2F3h ERR_OTHER_AP 2F4h RR_OTHER_CMOS...

  • Page 75: Appendix B: Interrupts

    Interrupts Appendix B The next table shows EPC-6315 interrupt assignments. This routing is implemented by the RadiSys 82600 embedded chipset. Table B-1. Interrupts Interrupt Description System timer (internal connection) IRQ0 Keyboard controller (internal connection) IRQ1 IRQ2 Cascade interrupt input (internal connection)
  • Page 76 ® -6315 Hardware Reference...

  • Page 77: Connector Locations

    The next figure shows the locations of connectors on the EPC-6315: Figure C-1. EPC-6315: connectors 3-pin connector Ethernet port CompactFlash socket Signals used for a purpose other than that identified in the appropriate specification are noted as follows: XYZ / NC RadiSys use Specified use...

  • Page 78: Compactpci Connector

    ® -6315 Hardware Reference CompactPCI connector J1 connector The CompactPCI J1 connector is a female 2mm-pitch 6 column by 25 row right angle Hard Metric (HM) connector with a guide lug in the center. Table C-1. CompactPCI J1 connector pin definitions –12V +12V NC (~TRST)

  • Page 79: Pmc Connectors

    Appendix C: Connectors PMC connectors The main board supports a backplane via standard Jn1 and Jn2 PMC connectors. The PMC site provides power for +3.3V, +5V, +12V and –12V. The PCI interface uses +3.3V signaling, but is +5V tolerant. This allows VIO to connect to +5V or +3.3V on the EPC-6315.56.

  • Page 80: Jn2 Connector

    ® -6315 Hardware Reference Jn2 connector Table C-3. Jn2 connector pin definitions Signal Signal +12V ~TRST PCI-Reserved ~SERIRQ/NC PCI-Reserved ~Busmode2 +3.3V ~RST ~Busmode3/NC +3.3V ~Busmode4/NC ~PME AD[30] AD[29] AD[26] AD[24] +3.3V IDSEL AD[23] +3.3V AD[20] AD[18] AD[16] C/~BE[2] IDSELB/NC ~TRDY +3.3V ~STOP ~PERR...

  • Page 81: Jn4 Connector

    Appendix C: Connectors Jn4 connector The PMC user-defined optional connector, Jn4, routes a set of standard peripheral signals such as EIDE, COM, keyboard, and mouse as well as PCI signals for four ~REQ/~GNT pairs and one BPCI clock. Table C-4. Optional JN4 connector pin definitions Signal Signal ~RST...

  • Page 82: Table C-5. Pmc Connector Jn4 Signal Summary

    ® -6315 Hardware Reference Table C-5. PMC connector Jn4 signal summary Signal name Type Description A[2:0] Primary disk address[2:0]. These signals indicate which byte in either the ATA command block or control block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected to the corresponding signals on the Primary IDE connector.
  • Page 83 Appendix C: Connectors Table C-5. PMC connector Jn4 signal summary Signal name Type Description ~DMACK Primary disk DMA request. This input signal is directly driven from the IDE device DMARQ signal. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function.
  • Page 84 ® -6315 Hardware Reference Table C-5. PMC connector Jn4 signal summary Signal name Type Description Primary disk IO write. In normal IDE mode, this is the command to the IDE device that it may latch data from the PDD[15:0] lines. Data is latched by the IDE device on the negation edge of ~PDIOW.

  • Page 85: Ethernet Port

    Appendix C: Connectors Ethernet port The front panel RJ45 connector provides support for 10/100Base-TX Ethernet channel. The RJ45 connector does not contain magnetics and LEDs. Table C-6. Ethernet pin definitions Description Description Transmit + Receive – Transmit – TERM Receive + TERM TERM Shield...

  • Page 86: 3-Pin Connector

    COM1:RXD For information about using this connector, see Using the 3-pin connector page 9. Null-modem serial cable RadiSys does not supply the serial cable. To assemble the cable, you will need the following: Item Part number 3-pin connector Molex receptacle 51021-0300...

  • Page 87: Appendix D: Error Messages

    Error messages Appendix D Upon encountering the following error conditions, the System BIOS tries to display a message on the VGA, and the console when redirected, then halts: The messages that can display depend upon your system’s configuration. For example, systems that do not have a floppy drive will not encounter a situation requiring a diskette error message.
  • Page 88 ® -6315 Hardware Reference...

  • Page 89: Appendix E: Flash Memory Addresses

    Flash memory addresses Appendix E The EPC-6315 flash chip contains these major sections: Figure E-1. Flash chip memory addresses Physical address Offset 0x0000 0000 128 Kbyte BLOCK 31 0xFFFE 0000 3E0000 BIOS 128 Kbyte BLOCK 30 0xFFFC 0000 3C0000 BIOS 128Kbyte BLOCK 29 0xFFFA 0000 3A0000...
  • Page 90 ® -6315 Hardware Reference...

  • Page 91: About The Flash Chip

    Re-programming the flash chip Appendix F This appendix details how to update or recover your Flash Boot Device (FBD). You accomplish this by re-programming all or part of the EPC-6315’s flash chip. When reading this file online, you can immediately view information about any topic by placing the mouse cursor over a task and clicking.

  • Page 92: About Re-Programming The Flash Chip

    Before you begin Ensure that you have the following: • Minimum 2 MB of DRAM to run the re-flash program. • A 3.5" 1.44 MB hard drive attached to or installed in the system. • Access to the RadiSys web site.

  • Page 93: Creating A Flash Boot Diskette

    To create the Flash Boot image on a hard drive: 1. Locate this file from the RadiSys web site and download it to your computer: fbdrec.zip 2. Unzip the contents to a directory on your hard drive.

  • Page 94: Using Phlash.exe To Re-Program The Flash Chip

    ® -6315 Hardware Reference Using phlash.exe to re-program the flash chip 1. Boot the EPC-6315 into MS-DOS with no memory managers running. 2. Copy the Flash Boot image to the system. For detailed information about creating a Flash Boot diskette, see Before you begin on page 82.

  • Page 95: Appendix G: Carrier Card Design

    Carrier card design Appendix G To use Monarch mode, you must design a carrier card that supports Monarch mode. The rest of this appendix provides guidelines for designing such a card. PrPMC connectors (Jn1 and Jn2) General Leave all reserve pins unconnected. The PCI:~RST signal is an input to the PrPMC.

  • Page 96: Jn1

    ® -6315 Hardware Reference Clocking The carrier card must provide clocking to the PrPCMC. RadiSys provides an alternative mechanism via Jn4. For more information, see the Jn4 description. Arbitration The carrier card must provide arbitration to the PrPCMC. RadiSys provides an alternative mechanism via Jn4.

  • Page 97: Serial Port

    Jn4 provides PWR_BAT_IN, a connection for the battery. The battery provides backup power to the BIOS CMOS settings for occasions when power is not applied. UL requires a 1K series resistor. RadiSys recommends isolating this from the +3V power supply with a low-leakage Schottky diode. RadiSys provides this series resistor and a low leakage Schottky resistor on the EPC-6315.

  • Page 98: Maximum Ambient Temperature

    Of particular interest to designers is that J1 provides user access to the serial port. This 5.7mm tall connector is located where Jn3 normally sits on a carrier card. If this conflict with your carrier card’s requirements, contact RadiSys. Maximum ambient temperature Maximum ambient temperature is 50°C at the EPC-6315.
  • Page 99 Appendix G: Carrier card design...
  • Page 100 ® -6315 Hardware Reference...
  • Page 101 Appendix G: Carrier card design...
  • Page 102 ® -6315 Hardware Reference...
  • Page 103 Appendix G: Carrier card design...
  • Page 104 ® -6315 Hardware Reference...
  • Page 105 Appendix G: Carrier card design...
  • Page 106 ® -6315 Hardware Reference...
  • Page 107 Appendix G: Carrier card design sheet 8...
  • Page 108 ® -6315 Hardware Reference Shield PMC SITE Shield Shield PMC SITE Shield Shield PMC SITE Shield...

  • Page 109: Features

    The EPC-6315 test board (hereafter, Test Board) is a full ATX-sized, four PMC site circuit board that you can use to begin production, test, and early development using the RadiSys EPC-6315 PrPMC. This product assumes an intimate knowledge of the PrPMC specification, the standards governing other external interfaces to the PrPMC, and basic computer knowledge.

  • Page 110: Specifications

    3-pin jumper for arbitration selection. Note: This feature does not operate. The only available arbitration selection is that the Test Board provides arbitration. If this presents a problem, contact RadiSys as described in Where to get more information on page iv.

  • Page 111: Block Diagram

    Appendix H: EPC-6315 test board Block diagram Figure H-1. Block diagram Slot 1: Slot 2: Site 3: 53C895 SCSI: KB, mouse, serial KB, mouse, serial 33/66MHz 33MHz only 40 & 44 pin IDE 40 & 44 pin IDE Jn1/Jn2 only battery battery Mon-Monarch only...

  • Page 112: Reset Switch

    Secondary PCI bus V I/O (1–2 +5V, 2–3 +3.3V) Artbiter select (Does not function) Pushbutton reset (RadiSys only) Reset (1–2 reset, 2–3 no reset) Primary PCI bus V I/O (1–2 +5V, 2–3 +3.3V) PCI Bus clock select 1–2 33MHz, 2–3 66MHz J41, J? Monarch –...

  • Page 113: Glossary

    Glossary A factor in measurement of a memory storage device’s operating speed. It is the access time amount of time required to perform a read operation. More specifically, it is the period of time between which the memory receives a read command signal and the time when the requested data becomes available to the system data bus.
  • Page 114 ® -6315 Hardware Reference A process whereby an existing, uncorrupted BIOS image in the flash boot device is BIOS update overwritten with a new image. Also referred to as a flash update. A binary digit. The process of starting a computer and loading the operating system from a powered boot down state (cold boot) or after a computer reset (warm boot).
  • Page 115 Glossary (Dual In-Line Package) A semiconductor package configuration consisting of a rectangular plastic case with two rows of pins, one row on each lengthwise side. (Disk Operating System) One or more programs which allow a computer to use a disk drive as an external storage device. These programs manage storage and retrieval of data to and from the disk and interpret commands from the computer operator.
  • Page 116 ® -6315 Hardware Reference See Brecovery. Flash recovery BIOS update. Flash update force See Brecovery. update (Field Programmable Gate Array) A large, general-purpose logic device that is FPGA programmed at power-up to perform specific logic functions. (Fast Page Mode) A “standard” type of DRAM that is lower performance than EDO.
  • Page 117 Glossary (Interrupt Service Routine) A program executed by the microprocessor upon receipt of an interrupt request from an I/O device and containing instructions for servicing of the device. A set of male connector pins on a circuit board over which can be placed coupling jumper devices to electrically connect pairs of the pins.
  • Page 118 ® -6315 Hardware Reference The address or location in memory where data is stored before it is moved as memory physical address remapping occurs. The physical address is that which appears on the computer’s address bus when the CPU requests data from a memory address. When remapping occurs, the data can be moved to a different memory location or logical address.
  • Page 119 Glossary The process of replacing a BIOS image, in binary format, in the flash boot device. reflashing An area typically inside the microprocessor where data, addresses, instruction codes, register and information on the status on various microprocessor operations are stored. Different types of registers store different types of information.
  • Page 120 ® -6315 Hardware Reference (Static Random Access Memory) A semiconductor RAM device in which the data SRAM remains permanently stored as long as power is applied, without the need for periodically rewriting the data into memory. A mechanical device, typically constructed of an electrically non-conductive standoff material, used to fasten a circuit board to the bottom, top, or side of a protective enclosure.

  • Page 121: Index

    Dynamic Random Access Memory (DRAM), defined boot device, defined sequence, defined Boot menu EDO DRAMs, defined Boot Options sub-menu electrostatic discharge, avoiding byte, configuration e-mail address, RadiSys EPC-6315 disconnecting from carrier card installing cable ESCD block serial port ESD, avoiding cache extended...
  • Page 122 Power-On Self Test (POST) mapping assignments defined request (IRQ), defined Power-On Self-Test (POST) Primary Slave sub-menu Jn1 connector Jn2 connector RadiSys, contacting Jn4 connector RAM, defined jumpers Random Access Memory (RAM), defined defined README file readme.txt file Real Mode Address, defined...
  • Page 123 BIOS, defined SIMMs flash, defined defined URLs symmetrically addressable, defined MontaVista Single In-Line Memory Module (SIMM), defined RadiSys WindRiver static-sensitive devices, handling User Editable Drive (UED), defined support Symmetrically Addressable SIMM, defined system BIOS, caching BIOS memory, amount displayed...

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