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RadiSys EPC-3307 Hardware Reference Manual

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Summary of Contents for RadiSys EPC-3307

  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 ® -3307 Hardware Reference www.radisys.com World Headquarters 5445 NE Dawson Creek Drive • Hillsboro, OR 97124 USA Phone: 503-615-1100 • Fax: 503-615-1121 Toll-Free: 800-950-0044 International Headquarters Gebouw Flevopoort • Televisieweg 1A NL-1322 AC • Almere, The Netherlands Phone: 31 36 5365595 • Fax: 31 36 5365620...
  • Page 3 Copyright ©2002 by RadiSys Corporation. All rights reserved. EPC, INtime, iRMX, and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ, MultiPro, SAIB, Spirit, and ValuePro are trademarks of RadiSys Corporation. DAVID, MAUI, OS-9, SoftStax, and OS-9000, are registered trademarks of RadiSys Microware Communications Software Division, Inc.

  • Page 4: Table Of Contents

    Chapter 2: Configuration and installation. Setting jumpers and headers ......................Flash ........................................................Inserting the EPC-3307........................Maintaining and upgrading the EPC-3307..................Removing the EPC-3307 ......................Replacing the battery ......................... Chapter 3: BIOS configuration. BIOS setup screens..........................Menu map..........................Navigation ..........................
  • Page 5 EPC-3307 Hardware Reference 440GX host bridge........................440GX PCI bus ........................DRAM/SDRAM memory controller ..................PIIX4E PCI-ISA bridge ....................... PCI-ISA bridge........................controller........................Compatibility devices......................Enhanced USB controller ..................... SMBus interface and implementation................... RTC............................. Intel 21554 PCI-PCI bridge ......................CPU board reset on host command over CompactPCI............
  • Page 6 Contents connector..........................connector..........................connector..........................PMC A connectors..........................J11 connector ..........................J12 connector ..........................J13 connector ..........................J14 connector ..........................PMC B connectors ..........................J21 connector ..........................J22 connector ..........................connector..........................IDE (primary) ........................... 100. Memory card connectors ........................101..............................101.
  • Page 7 EPC-3307 Hardware Reference Creating a Flash Boot diskette ......................127. Using phlash.exe to re-program the flash chip .................. 129. Using BIOS configuration options to re-program the flash chip ............130. Using jumpers to re-program the flash chip ..................131. Glossary.
  • Page 8 Contents Figures Figure 1-1. The EPC-3307........................Figure 2-1. EPC-3307 CPU board: jumper locations ................Figure 2-2. Flash header settings ......................Figure 3-1. BIOS Main Setup menu......................Figure 3-2. Primary/Secondary Master/Slave sub-menus................Figure 3-3. Keyboard Features sub-menu ....................Figure 3-4. UBE Shadow Control sub-menu....................
  • Page 9 EPC-3307 Hardware Reference Tables Table 1-1. EPC-3307 environmental specifications.................. Table 4-1. 440GX unsupported commands ..................... Table 4-2. T8105 summary ........................Table 4-3. T8105 I/O map........................Table 4-4. T8105 signals ......................... Table 4-5. T8105 clock sources ....................... Table 4-6. PCI device configuration......................
  • Page 10 104. Table C-18. RJ45 phone jack pin-out ...................... 104. Table C-19. RJ45 phone jack pin-out ...................... 104. Table E-1. EPC-3307 Rear Transition module: block diagram ..............110. Table E-2. Backplane connector J3 ......................114. Table E-3. Backplane connector J5 ......................
  • Page 11 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 12 Before you begin This guide provides the information you need to install the EPC-3307 and configure its BIOS. It contains detailed hardware reference information for OEMs, system integrators, and others who use the EPC-3307 as a component of their †...
  • Page 13 You can find out more about EPC-3307 from these sources: • World Wide Web: RadiSys maintains an active site on the World Wide Web. The site contains current information about the company and locations of sales offices, new and existing products, contacts for sales, service, and technical support information.

  • Page 14: Chapter 1: Overview

    Overview Chapter 1 † The EPC-3307, a CompactPCI Peripheral Processor Board, operates in a 6U peripheral slot of a CompactPCI system. The EPC-3307 hardware is compatible with all major PC software environments † † † including Microsoft Windows 95, Windows 98, and Windows NT 4.0.

  • Page 15: Feature Summary

    PMC slot 2 • One PMC. • Up to 2 memory modules. The EPC-3307 can be fitted with a PMC module, a PCI Mezzanine card that conforms to IEEE P1386.1. For more information about PMC modules, see Appendix F, PMC modules.
  • Page 16 Watchdog timer with programmable timeouts which you can program to produce hard or soft resets. The EPC-3307 can accept the RadiSys memory module, available in 256 MByte, 512MByte, and 1GByte densities. You can stack two memory cards on the main board, although you can use only one of each memory module density.

  • Page 17: Compactpci Bus

    CompactPCI backplane. CompactPCI bus The CompactPCI bus is accessed from the EPC-3307’s PCI bus via an Intel 21554 PCI-to-PCI bridge. This bridge connects the onboard PCI bus (bus 0) with the CompactPCI bus, which may have as many as seven additional CompactPCI devices connected to it.
  • Page 18 (2000m) with sufficient airflow to keep within the temperature specification. Operation above 30°C reduces the maximum operational relative humidity. These are system-level tests. The EPC-3307’s conformance to these specifications may be affected by the rest of the system’s ability to conform. Since the product is part of a larger system, it is designed and tested to these specifications, but not agency certified.
  • Page 19 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 20 Configuration and installation Chapter 2 This chapter explains how to install the EPC-3307 in a CompactPCI chassis. When reading this file online, you can immediately view information about any installation topic by placing the mouse cursor over a connector name and clicking.

  • Page 21: Setting Jumpers And Headers

    EPC-3307 Hardware Reference Setting jumpers and headers Flash Battery: Figure 2-1. EPC-3307 CPU board: jumper locations Jumper pins are labeled from the point of view of looking at the front of the connector. Flash The CPU board provides a 2x5-pin header (H2) that you use to re-program the Flash chip.

  • Page 22: Mfg

    3. Slide the EPC-3307 module into the slot. Use firm pressure on the handles to mate the module with the connectors and snap connectors into normal position.

  • Page 23: Maintaining And Upgrading The Epc-3307

    2. Pull outward on the extractor handles until the EPC-3307 disengages from the rear connector. 3. Slide the EPC-3307 out of the CompactPCI chassis and place it in the anti-static bag that it came in. Replacing the battery 1.
  • Page 24 There is danger of explosion if battery is incorrectly replaced. Replace only with same or equivalent type recommended by RadiSys. Dispose of used batteries according to manufacturer’s instructions. 6. Replace the EPC-3307 in the CompactPCI chassis as described in Inserting the EPC-3307.
  • Page 25 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 26: Chapter 3: Bios Configuration

    BIOS configuration Chapter 3 The EPC-3307 uses the Phoenix NuBIOS to configure and select various system options. This chapter details the various menus and sub-menus used to configure the system. This chapter is written as though you are setting up each field in sequence and for the first time.

  • Page 27: Menu Map

    EPC-3307 Hardware Reference Menu map You set up the BIOS by making selections from the menus shown in the next table. When reading this file online, you can immediately view information about any menu by placing the mouse cursor over menu name and clicking:...

  • Page 28: Main Setup Menu

    Chapter 3: BIOS configuration Main Setup menu PhoenixBIOS Setup Utility Main Main Advanced Boot Exit System Time: [16:17:18] Item Specific Help System Date: [01/01/1997] <Tab>, <Shift-Tab>, or <Enter> selects field. BIOS Version 01.00.00 Legacy Diskette A: [1.44/1.25 MB 3½”] Legacy Diskette B: [Disabled] Primary Master [None]...

  • Page 29: Primary/Secondary Master/Slave Sub-Menus

    EPC-3307 Hardware Reference Field Description LegacyDiskette A Identifies the type of floppy disk drive installed as the A: or LegacyDiskette B B: drive. Possible settings include: • Disabled (default for the B: drive) • 1.44/1.25MB 31/2" (default for the A: drive) Note: The 1.25MB 31/2"...

  • Page 30: Figure 3-2. Primary/Secondary Master/Slave Sub-Menus

    Chapter 3: BIOS configuration Access this screen to: • See or reconfigure the detailed characteristics of the primary hard disk (select the IDE Adapter 0 Master item from the Main BIOS Setup). • Set up new disks and allow the Setup program to determine the proper settings based on information on the disk.
  • Page 31 EPC-3307 Hardware Reference Field Description Type Identifies the disk type. You can select one of these: • Auto (default): Select this option when you want the POST to query the hard disk for its parameters whenever the POST runs. Note: If you set a hard disk to “Auto”, but no hard disk is...
  • Page 32 Chapter 3: BIOS configuration Field Description Multi-Sector Transfers Allows the System BIOS to read ahead by the specified number of sectors during disk access. This has the effect of reading more data at once to reduce the absolute number of discrete disk reads performed by the operating system, which may increase system performance.
  • Page 33 EPC-3307 Hardware Reference Field Description Transfer Mode Selects the mode that the System BIOS uses to access the hard disk. You can select one of these: • Standard (default) • Fast PIO 1 • Fast PIO 2 • Fast PIO 3 •...

  • Page 34: Keyboard Features Sub-Menu

    Chapter 3: BIOS configuration Keyboard Features sub-menu Use this sub-menu to enable or disable various keyboard features. PhoenixBIOS Setup Utility Main Main Keyboard Features Item Specific Help NumLock: [Auto] <Tab>, <Shift-Tab>, or <Enter> Key Click: [Disabled] selects field. Keyboard auto-repeat rate: [30/sec] Keyboard auto-repeat delay: [1/2 sec]...
  • Page 35 EPC-3307 Hardware Reference Field Description Keyboard auto-repeat rate Sets the auto-repeat rate when holding a key down on the keyboard. You can select one of these: • 30/sec (default) • 26.7/sec • 21.8/sec • 18.5/sec • 13.3/sec • 10/sec • 6/sec •...

  • Page 36: Ube Shadow Control Sub-Menu

    Chapter 3: BIOS configuration UBE Shadow Control sub-menu Use this menu to specify BIOS shadow options. Shadowing refers to the technique of copying BIOS extensions from ROM into DRAM and accessing them from DRAM. This allows the CPU to access the BIOS extensions much more quickly and generally increases system performance if many calls to the BIOS extensions are made.
  • Page 37 EPC-3307 Hardware Reference Field Description BIOS Extension Source Controls the location of the user BIOS extension to shadow. Offset You can select one of these: • Disabled (default) • E000h • 0000h 10000h • • 2000h 12000h • • 4000h •...

  • Page 38: Advanced Menu

    Chapter 3: BIOS configuration Advanced menu This menu contains settings for integrated peripherals, memory shadow, cache, and large disk access mode. You access this menu by selecting Advanced from the Main BIOS Setup menu. PhoenixBIOS Setup Utility Main Main Advanced Boot Exit BIOS Reboot:...
  • Page 39 EPC-3307 Hardware Reference Field Description T810x Data: Determines how to handle data latched on non-written timeslots. You can select one of these: • Weak Keeper (default): Does not propagate latched data to other timeslots. • Strong Keeper: Propagates latched data to other timeslots.
  • Page 40 Chapter 3: BIOS configuration Field Description Reset Configuration Data Determines whether to clear the Extended System Configuration Data (ESCD) block that resides in the Flash Boot Device (FBD). You can select one of these: • No (default): Does not clear the ESCD block. •...
  • Page 41 EPC-3307 Hardware Reference Field Description Local Bus IDE Adapter Configures the integrated local bus IDE adapter. You can select one of these: • Both (default) • Disabled • Primary • Secondary Advanced Chipset Control Displays a menu that you use to control chip behavior. For...

  • Page 42: Console Redirection Sub-Menu

    Chapter 3: BIOS configuration Console Redirection sub-menu Options in this menu configure console redirection. PhoenixBIOS Setup Utility Main Advanced Com Port Address [On-board COM A] Item Specific Help <Tab>, <Shift-Tab>, or <Enter> Baud Rate [38.4K] selects field. Console Type [PC ANSI] Flow Control [CTS/RTS] Console connection:...
  • Page 43 EPC-3307 Hardware Reference Field Description Flow Control Specifies flow control. You can select one of these: • CTS/RTS (default) • XON/XOFF • None Console connection Specifies how the console connects to the system. You can select one of these: • Direct (default): Connects the console directly to the system.

  • Page 44: I/O Device Configuration Sub-Menu

    Chapter 3: BIOS configuration I/O Device Configuration sub-menu Use the options in this sub-menu to configure the onboard serial and parallel port and disk controllers. PhoenixBIOS Setup Utility Main Advanced I/O Device Configuration Item Specific Help Serial port A: [Enabled] <Tab>, <Shift-Tab>, or <Enter>...
  • Page 45 EPC-3307 Hardware Reference Field Description Base I/O Address Configures the base address for the serial port. If you select a value already used by another serial port, an asterisk displays at the left side of the screen. You can select one of these: •...

  • Page 46: Pci Configuration Sub-Menu

    Chapter 3: BIOS configuration PCI Configuration sub-menu Use the options in this sub-menu to control the exclusion of the UMB region for PCI or ISA and the exclusion of the IRQs for PCI or ISA. PhoenixBIOS Setup Utility Main Advanced PCI Configuration Item Specific Help ISA graphics device installed:...

  • Page 47: Cache Memory Sub-Menu

    EPC-3307 Hardware Reference Cache Memory sub-menu The options in this sub-menu control the cacheability of certain memory regions and also the settings of the Level 2 (L2) cache. PhoenixBIOS Setup Utility Main Advanced Memory Cache Item Specific Help Memory Cache: [Enabled] <Tab>, <Shift-Tab>, or <Enter>...
  • Page 48 Chapter 3: BIOS configuration Field Description Cache Base 0–512k Determines how the system caches base memory in the Cache Base 512– specified area: 640k You can select one of these: • Write Back (default): Writes and reads to and from system memory are cached, then written to system memory when you perform a write-back operation.
  • Page 49 EPC-3307 Hardware Reference Field Description Cache Memory Regions: Determines how the system deals with specified memory blocks or shadow memory. You can select one of these: A000–AFFF B000–BFFF • Disabled (default): The system does not cache memory. • USWC Caching: System memory locations are not cached (as with uncacheable memory) and coherency is not enforced by the processor’s bus coherency protocol.
  • Page 50 Chapter 3: BIOS configuration Field Description Cache Memory Regions: Memory regions. C800–CBFF Determines how the system deals with specified memory CC00–CFFF blocks or shadow memory. You can select one of these: D400–D7FF • Disabled (default): The system does not cache memory. D800–DBFF •...
  • Page 51 EPC-3307 Hardware Reference Field Description Cache Memory Regions: Memory used in the E0000h–EFFFFh DRAM region. E000–E3FF Determines how the system deals with specified memory E400–E7FF blocks or shadow memory. You can select one of these: E800–EBFF • Disabled (default): The system does not cache memory.

  • Page 52: Advanced Chipset Control Sub-Menu

    Chapter 3: BIOS configuration Advanced Chipset Control sub-menu Options in this menu control error checking. PhoenixBIOS Setup Utility Main Advanced ECC Config: [ECC] Item Specific Help <Tab>, <Shift-Tab>, or <Enter> selects field. ↑↓ Help Select Item Change Values Setup Defaults ←→...

  • Page 53: Boot Menu

    EPC-3307 Hardware Reference Boot menu The Boot menu: • Specifies the order in which the system tries to boot from devices attached to the system. • Specifies the boot order of devices in the same class, such as hard drives.

  • Page 54: Exit Menu

    Chapter 3: BIOS configuration Field Description Boot order Determines the boot order of boot devices. This is the default boot order: 1. Hard Drive 2. Removable Devices 3. ATAPI CD-ROM Drive 4. Network Boot 5. MBA UNDI (Bus 0 Slot 2) 6.
  • Page 55 EPC-3307 Hardware Reference Field Description Load Setup Values Resets the BIOS values to the original, default values set at the factory, before any suppliers or other end users made changes. Discard Changes Loads the system with the values that existed before this editing session started.

  • Page 56: Cmos Save And Restore Sub-Menu

    Chapter 3: BIOS configuration CMOS Save and Restore sub-menu Use the options in this menu to save, restore, or erase CMOS settings in the FBD (Flash Boot Device). PhoenixBIOS Setup Utility Main Exit CMOS Save & Restore Item Specific Help <Tab>, <Shift-Tab>, or <Enter>...
  • Page 57 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 58 Windows NT 4.0. It can also run other PC operating systems, including Linux, Solaris, and DOS. When reading this file online, you can immediately view information about any EPC-3307 topic by placing the mouse cursor over the topic name and clicking: For information about... Go to this page...

  • Page 59: Organization

    Figure 4-1. EPC-3307: block diagram Features CPU module The EPC-3307’s design centers on an Intel BGA2 mobile processor which includes a a 700MHz Intel Pentium III processor, 100 MHz Front Side Bus plus a 256kbyte on-die cache. The CPU bus frequency is 100MHz.

  • Page 60: Memory Map

    FFF00000–FFFFFFFF Flash memory If no BIOS extensions, ISA bus (aliased); not cacheable. If no DRAM, ISA bus (aliased); not cacheable. Interrupt usage For details about EPC-3307 PC-compatible interrupt usage, see Appendix B, Interrupts. Flash boot device A Boot Block Flash memory stores system start-up code for the CPU board. This...

  • Page 61: Bios Rom And Rom Shadowing

    FFF80000h–FFFFFFFFh. BIOS ROM and ROM shadowing The EPC-3307 utilizes a Flash Boot Device (FBD) as its BIOS ROM. The BIOS ROM is mapped into the top of the processor’s 32-bit address space. The BIOS consists of a 16 KByte boot block and the System BIOS in the 96KB Main block and both 8KB parameter blocks.

  • Page 62: 440Gx Host Bridge

    Chapter 4: Theory of operation Physical address Device offset FFFFFFFFh 16 KB FFFFFh FFFFC000h BIOS Recovery Code FC000h FFFFBFFFh 8 KB Parameter Block 2 FBFFFh FFFFA000h ESCD FA000h FFFF9FFFh 8 KB Parameter Block 1 F9FFFh FFFF8000h F8000h FFFF7FFFh 96 KB Main Block 8 F7FFFh FFFE0000h System BIOS, PCI BIOS,...

  • Page 63: Dram/Sdram Memory Controller

    Supports five PCI bus masters in addition to the Host and PCI to ISA bridge DRAM/SDRAM memory controller The 440GX supports 100 MHz SDRAM memory. The EPC-3307 uses both soldered-down memory and the RadiSys Blue Heron memory module. All memory configurations are with ECC.

  • Page 64: Piix4E Pci-Isa Bridge

    Chapter 4: Theory of operation PIIX4E PCI-ISA bridge The Intel PIIX4E is a 324-pin BGA that runs on +3.3V with a reference voltage tied to +5V for +5V signal compatibility. It dissipates a maximum of 1 W. The PIIX4E provides support for a PCI-to-ISA bridge, an IDE controller, compatibility devices, a dual USB controller, SMBus, a real time clock (RTC), and power management logic.

  • Page 65: Enhanced Usb Controller

    EPC-3307 Hardware Reference • Distributed DMA: Allows PCI devices to receive reads and writes to 82C37 registers. The DMA controller also provides support for the serial interrupt scheme typically associated with Distributed DMA. • Timer/counters: The timer/counter block contains three counters equivalent in function to those found in one 82C54 programmable interval timer.

  • Page 66: Intel 21554 Pci-Pci Bridge

    Chapter 4: Theory of operation format is determined by bit 2 of Control Register B. The hour is represented in 12- or 24-hour format, and the format is selected by bit 1 of Control Register B. When changing the format, the time registers must be reinitialized to the corresponding data format.

  • Page 67: Cpu Board Reset On Host Command Over Compactpci

    EPC-3307 Hardware Reference mapping requirements, Class Code, Subsystem ID and Subsystem Vendor ID, and others. During the preload operation, all accesses to the 21554 configuration registers receive a target retry. CPU board reset on host command over CompactPCI The CPU board may be reset independently of other system peripherals by the System Slot CPU.

  • Page 68: H.110 Telephony Interface

    • H.110 Bus on J4 • PMC J13 The PMC site on the EPC-3307 is pin-compatible with the RadiSys ARTIC 4-port T1/E1//J1 DSP PMC. Rear I/O is available for the PMC on J14. PMC AI13 Local serial eight pairs T8105 H.110...

  • Page 69: Table 4-4. T8105 Signals

    EPC-3307 Hardware Reference Table 4-4. T8105 signals Clocks and frames Connection Notes XTALIN 16.384MHz clock 4Mhz in Gatted PRIREFOUT PRIREFOUT is gated by a quickswitch. Set GP0 low to pass clock to 4MHz in. 3Mhz in No connect Unused L_REF0...

  • Page 70: General Purpose I/Os

    Chapter 4: Theory of operation General purpose I/Os The T8105 includes these General Purpose (GP) I/Os: Signal Default Default Name Value Function Function T8105:PRIREFOUT_~OE Enables the primary ref out Primary reference out is (P5) to 4MhzIN (U2). isolated from 4MhzIN Unused –...

  • Page 71: 5.0V Pmc Site

    CompactPCI ENUM. The ENUM signal is bussed on the cPCI backplane and is asserted when any card (including the EPC-3307) in the system requests enumeration or to be taken off-line. The interrupt is enabled in the CPLD.

  • Page 72: Pci Bus Implementation And Devices

    Chapter 4: Theory of operation PCI bus implementation and devices The CPU board implements a +3.3V (5V tolerant), 32-bit local PCI bus. The bus runs at 33 MHz and has the 440GX as the central resource. The local PCI bus has these peripherals connected to it: •...

  • Page 73: Battery

    RTM near the RJ45. Battery The 3.0V lithium battery supplied with the EPC-3307 and mounted on the CPU board is a Renata CR2032 “coin cell” or equivalent. Should the battery fail, you may obtain and install a replacement.

  • Page 74: Com Ports

    PICMG 2.9 R1.0 CompactPCI System Management Specification. This IPMI BMC provides the ability to monitor, query, and log system management events on the EPC-3307 and in the CompactPCI system. This capability provides the ability to detect failing hardware, log the sequence of events leading to a failure and remotely manage and reset the system.

  • Page 75: Hdd Option

    EPC-3307 Hardware Reference HDD Option The EPC-3307 can accept an on-board 2.5" HDD. The HDD is mounted to the CPU with rails, which mount to PMC mounting holes. The HDD attaches to the main board with a standard 2mm ribbon cable.

  • Page 76: Watchdog Timer

    0x0F RTM Version 0x10 Allows CPU to determine which RTM is presently installed. Subsystem ID 0x11 EPC-3307 subsystem ID (0x1F). Reserved 0xFF — — Software must first write to the index register before reading or writing to the data register.

  • Page 77: Front Panel Red/Green Led

    EPC-3307 Hardware Reference Application software can prevent the watchdog event from occurring by a dummy write (data written is irrelevant) to the Kickdog register. On a soft reset, the Watchdog Central register resets to 0x00. This is the only register in the CPLD (other than the Reset Event register) affected by a soft reset.

  • Page 78: Last Reset Source

    Indicates that the last reset was from the Watchdog timer, active high. Local interrupt control register The EPC-3307 Special Features CPLD controls several interrupts and the CPU INIT signal. The Local Interrupt Control register enables or disables these signals. The next table defines the bit position to control these features.

  • Page 79: Reset Controller

    63 ms before the INIT signal to the processor is strobed. Reset controller The EPC-3307 implements three types of resets: POR, Hard Reset, and Soft Reset. A POR and Hard Reset are identical: all registers are set to their initial value (with the exception of the Reset Event register which retains the source of the hard reset).

  • Page 80: Hot Swap Signals

    (if required) the source of the interrupts. Slot position can be determined by reading the Geographical Address from the CPLD. Plug the EPC-3307 into a system slot only if the system is specifically designed around the EPC-3307 feature set. The EPC-3307 is not designed as a system card.

  • Page 81: Ipmi Special Utility

    EPC-3307 Hardware Reference system. INTS_IN Routes CompactPCI interrupts to the processor. If set to one, the CPU receives ~INTA , ~INTB, ~INTC, and ~INTD from the CompactPCI backplane. GA4:0 The CompactPCI Geographical Address pins from the CompactPCI backplane. They are used to determined which CompactPCI slot the CPU is in.

  • Page 82: Figure 4-3. Bios Paging

    Chapter 4: Theory of operation register in the CPLD controls which page is active. On initial power-up, the BIOS Control register is set to point at the top of the boot block flash, where the PC BIOS resides. At a later time, software can select one of the other seven banks to execute from.

  • Page 83: Power Monitoring, Consumption, And Reset Generation

    EPC-3307 Hardware Reference Table 4-19. Flash banks Page 512k user space 512k user space Power monitoring, consumption, and reset generation The CPU board includes: • Power conditioning: provides live insertion and removal without damage. • Board input voltage monitoring: ensures operation within a legal voltage range.
  • Page 84 Chapter 4: Theory of operation On the component side, the maximum height dictated by PICMG 2.0 CompactPCI Specification R3.0 is 13.71 mm. The CPU/heat sink and the hard disk drive/bracket assemblies exceed this height limit. The heat sink and CPU combined height is 15.00 mm and the hard disk drive/bracket assembly is 14.77 mm.
  • Page 85 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 86: Appendix A: Chipset And I/O Map

    Appendix A This appendix contains the port I/O addresses for the address-mapped devices in the EPC-3307. As is standard for the ISA bus, the A[15:0] bits are decoded for the 0200h 03FFh range and A[15] and A[9:0] are decoded for addresses above 8000h.

  • Page 87: Table A-4. Time/Counter Functions

    EPC-3307 Hardware Reference Table A-4. Time/counter functions I/O Addr Functional group Usage 0040 Timer/counter Counter 0 count 0041 Counter 1 count 0042 Counter 2 count 0043 Command mode Table A-5. Keyboard controller I/O Addr Functional group Usage 0060 Keyboard Data I/O register...

  • Page 88: Table A-8. Dma Page Registers: Intel Ex 82371Eb Of Pc/At ................................................................. Table A-9. Port A

    Appendix A: Chipset and I/O map Table A-8. DMA page registers: Intel EX 82371EB of PC/AT I/O Addr Functional group Usage 0080 DMA page (reserved) 0081 DMA channel 2 page register 0082 DMA channel 3 page register 0083 DMA channel 1 page register 0084 DMA page (reserved) 0085...

  • Page 89: Table A-13. Second (16-Bit) Dma Controller

    EPC-3307 Hardware Reference Table A-13. Second (16-bit) DMA controller I/O Addr Functional group Usage 00C0 DMA controller 2 DMA 2 channel 4 address 00C2 DMA 2 channel 4 count 00C4 DMA 2 channel 5 address 00C6 DMA 2 channel 5 count...

  • Page 90: Table A-17. Cpld

    Appendix A: Chipset and I/O map Table A-17. CPLD I/O Addr Functional group Usage 0180 CPLD, T8105 Table 4-7, CPLD I/O ports – 018F page Table A-18. Primary IDE I/O Addr Functional group Usage 01F0 Primary IDE Data 01F1 Error/features 01F2 Sector count 01F3...

  • Page 91: Table A-22. Serial I/O (Com 2) Port

    EPC-3307 Hardware Reference Table A-22. Serial I/O (COM 2) port I/O Addr Functional group Usage x2F8 COM 2 serial port Receiver buffer Transmitter buffer Baud rate divisor latch (LSB) x2F9 Interrupt enable register Baud rate divisor latch (MSB) x2FA Interrupt ID register...
  • Page 92 Appendix A: Chipset and I/O map Table A-27. EGA controller I/O Addr Functional group Usage x3C0 EGA controller Attribute controller index/data x3C1 Attribute controller index/data x3C2 Input status register 0 Miscellaneous output x3C3 Motherboard sleep x3C4 Sequencer index x3C5 Sequencer data x3C6 Video DAC pixel mask Hidden DAC register...
  • Page 93 EPC-3307 Hardware Reference Table A-31. Primary IDE I/O Addr Functional group Usage x3F6 Primary IDE Alternate status/device control x3F7 Digital input register Configuration control register Table A-32. Serial I/O (COM 1) port I/O Addr Functional group Usage x3F8 COM 1 serial port...
  • Page 94 Appendix A: Chipset and I/O map Table A-36. 443BX configuration address register I/O Addr Functional group Usage 0CF8– 443GX configuration Configuration address register 0CFB address register Table A-37. PIIX4E I/O Addr Functional group Usage 0CF9 PIIX4E Turbo reset control register Table A-38.
  • Page 95 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 96: Appendix B: Interrupts

    Interrupts Appendix B The following table shows interrupt assignments for the EPC-3307. Table B-1. Interrupts Interrupt Description IRQ0 System timer (internal PIIX4E connection) IRQ1 Keyboard controller IRQ2 Cascade interrupt input (internal PIIX4E connection) IRQ3 COM 2 IRQ4 COM 1 IRQ5...
  • Page 97 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 98 Connectors Appendix C This appendix details the connectors on the EPC-3307 CPU board and gives the signal pinout of each connector. For more information about connectors on the RTM, see Appendix E, Rear Transition module (RTM). This product includes the connectors listed in the table below. When reading this file online, you can immediately view information about any connector by placing the mouse cursor over a connector name and clicking.

  • Page 99: Appendix C: Connectors

    EPC-3307 Hardware Reference Connector locations Figure C-1 shows the locations of the connectors on the EPC-3307’s CPU board. For information about installing peripherals and jumper settings, see Chapter 2, Configuration and installation. PMC A connectors IDE (primary) Memory card connectors...

  • Page 100: Compactpci Connectors

    Appendix C: Connectors CompactPCI connectors J1 connector The CompactPCI J1 connector is a female 2mm-pitch 6 column by 25 row right angle Hard Metric (HM) connector with a guide lug in the center. Table C-1. CompactPCI J1 connector –12V +12V NC (~TRST) NC (TCK) NC (TMS)

  • Page 101: J2 Connector

    EPC-3307 Hardware Reference J2 connector The CompactPCI J2 connector is exactly the same as the J1 connector except there are only 22 rows numbered 1 22, and the center guide lug is eliminated. All these – signals have the standard CompactPCI revision 2.1 bus definitions.
  • Page 102 Appendix C: Connectors Connector P2 pin C2 is grounded at the System Slot only. Remaining slots leave C2 unconnected. Boards that use this signal (e.g., CPU boards that may be used in the System Slot or Peripheral Slot) shall provide a local pullup to V(I/O). System Slot only boards should tie this pin directly to the ground plane.
  • Page 103 EPC-3307 Hardware Reference J3 connector The J3 connector specified in CompactPCI is a female 2mm-pitch 6 column by 19 Backplane J3 row right angle Hard Metric (HM) connector. The signals on this connector are proprietary and include the USB port, COM1 and COM2 ports, and PMC socket B I/O signals.
  • Page 104 Appendix C: Connectors J4 connector Table C-4. CompactPCI connector J4 Pin A CT_D0 +3.3V CT_D1 CT_D2 CT_D3 CT_D4 CT_D5 CT_D6 CT_D7 CT_D8 CT_D9 CT_D10 SCLKx2 CT_D11 CT_D12 +3.3V SCLK CT_D13 CT_D14 CT_D15 +3.3V CT_NETREF2 GND CT_D16 CT_D17 CT_D18 CT_NETREF1 GND CT_D19 CT_D20 CT_C8_B...
  • Page 105 EPC-3307 Hardware Reference J5 connector The back plane connector J5 routes both Ethernet channels, keybard and mouse, secondary EIDE, and PMC socket A I/O signals to the CompactPCI backplane. The next table shows this connector’s pinout. Table C-5. CompactPCI connector J5...
  • Page 106 Appendix C: Connectors PMC A connectors J11 connector Table C-6. J11 pinout (32-bit local PCI) Signal Signal N.C. (TCK) –12V PMC:~INTA PMC:INTB PMC:~INTC PMCA:~BUSMODE1 PMC:~INTD No connect No connect LPCI:CLK PMC:~GNT PMC:~REQ V(I/O)(+3.3V) LPCI:AD[31] LPCI:AD[28] LPCI:AD[27] LPCI:AD[25] LPCI:C/~BE[3] LPCI:AD[22] LPCI:AD[21] LPCI:AD[19] V(I/O)(+3.3V) LPCI:AD[17]...
  • Page 107 EPC-3307 Hardware Reference J12 connector Table C-7. J12 pinout (32-bit local PCI) Signal Signal +12V No connect (~TRST) No connect (TMS) No connect (TDO) No connect (TDI) No connect No connect No connect PMCA:~BUSMODE2 +3.3V LPCI:~RST PMCA:~BUSMODE3 +3.3V PMCA:~BUSMODE4 No connect...
  • Page 108 Appendix C: Connectors J13 connector Table C-8. J13 pinout (PMC-to-T8105 local streams) Signal Signal TDM:LDO[0] No connect TDM:LDI[0] TDM:LDO[1] TDM:LDI1[] TDM:LDO[2] No connect TDM:LDO[3] TDM:LDI[2] TDM:LDI[3] TDM:LDO[8] TDM:LDI[8] TDM:LDO[9] No connect No connect TDM:LDI[9] TDM:LDO[10] TDM:LDI[10] No connect TDM:LDI[11] No connect No connect TDM:L_REF[0] No connect...
  • Page 109 EPC-3307 Hardware Reference J14 connector Table C-9. J14 pinout (PMC-to-RTM’s PIM connector) Signal Signal J5-E13 J5-D13 J5-C13 J5-B13 J5-A13 J5-E12 J5-D12 J5-C12 J5-B12 J5-A12 J5-E11 J5-D11 J5-C11 J5-B11 J5-A11 J5-E10 J5-D10 J5-C10 J5-B10 J5-A10 J5-E09 J5-D09 J5-C09 J5-B09 J5-A09 J5-E08...
  • Page 110 Appendix C: Connectors PMC B connectors J21 connector Table C-10. J21 pinout (32-bit local PCI) Signal Signal N.C. (TCK) –12V PMC:~INTA PMC:INTB PMC:~INTC PMCB:~BUSMODE1 PMC:~INTD No connect No connect LPCI:CLK PMC:~GNT PMC:~REQ V(I/O)(+3.3V) LPCI:AD[31] LPCI:AD[28] LPCI:AD[27] LPCI:AD[25] LPCI:C/~BE[3] LPCI:AD[22] LPCI:AD[21] LPCI:AD[19] V(I/O)(+3.3V) LPCI:AD[17]...
  • Page 111 EPC-3307 Hardware Reference J22 connector Table C-11. J22 pinout (32-bit local PCI) Signal Signal +12V No connect (~TRST) No connect (TMS) No connect (TDO) No connect (TDI) No connect No connect No connect PMCB:~BUSMODE2 +3.3V LPCI:~RST PMCB:~BUSMODE3 +3.3V PMCB:~BUSMODE4 No connect...
  • Page 112 Appendix C: Connectors J24 connector J24 allows rear I/O to the RTM. On a standard RTM, these signals are not used. The IDE-Primary signals and the Floppy signals are disconnected from the circuit path by not installing zero ohm rsistors. Therefore, this configuration only supports the floppy connected to the CPU board.
  • Page 113 EPC-3307 Hardware Reference IDE (primary) The secondary IDE connector is a male 44-pin right-angle header located on the EPC-3307. The pins and signals are defined as: Table C-13. Primary IDE connector Signal Signal IDE:~RST IDE:D7 IDE:D8 IDE:D6 IDE:D9 IDE:D5 IDE:D10...
  • Page 114 Appendix C: Connectors Memory card connectors Table C-14. J9 (connector A, Blue Heron memory card) Signal Signal +3.3V DQ32 DQ33 DQ34 DQ35 +3.3V DQ36 DQ37 DQ38 DQ39 +3.3V DQ40 DQ41 DQ10 DQ42 DQ11 DQ43 +3.3V DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47...
  • Page 115 EPC-3307 Hardware Reference Table C-15. Connector A, Blue Heron memory card Signal Signal BA0 (A12) BA1 (A13) A12 (A14) +3.3V CKE0_LWR CKE1_LWR CKE0_UPR CKE1_UPR Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 116 Appendix C: Connectors Table C-16. J8 (connector B, Blue Heron memory card) Signal Signal +3.3V DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 +3.3V ~RAS ~CAS ~CS1_LWR ~CS0_LWR ~CS1_UPR ~CS0_UPR +3.3V DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 +3.3V DQ20 DQ52 DQ21...

  • Page 117: Ethernet (Optional)

    EPC-3307 Hardware Reference Table C-17. Connector B, Blue Heron memory card Signal Signal SMBCLK UPR_2BKS_~1BNK SMBDAT LWR_2BKS_~1BNK Reserved SPARE1 SA0_LWR SA1_LWR SA0_UPR SA1_UPR +3.3V Ethernet (optional) The DTE RJ-45 phone jack provides support for one 10/100BASE-T Ethernet channel. Table C-18. RJ45 phone jack pin-out...

  • Page 118: Front Panel

    Appendix C: Connectors Front panel LEDs Color Description Swap-ready Blue Indicates that it is safe to eject the CPU board. The ejector handle switch must be activated first then, after the OS has been notified, the OS illuminates the LED, indicating it is safe to pull the CPU board out from the chassis.
  • Page 119 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 120 Error messages Appendix D Boot failures The System BIOS attempts to display an error message on the VGA and halts when it encounters the following error conditions: 1. Fixed disk error • No drive connected • Configured for 0 cylinders •...
  • Page 121 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 122 Rear Transition module (RTM) Appendix E This appendix describes the Rear Transition module (RTM), a single slot rear I/O module which connects to the backside of the J3 and J5 connectors, directly behind the CPU board. This appendix includes the topics listed in the table below. When reading this file online, you can immediately view information about any topic by placing the mouse cursor over a connector name and clicking.
  • Page 123 SEC IDE USB 2 COM 1 USB 1 COM 2 REAR I/O Table E-1. EPC-3307 Rear Transition module: block diagram CPU board I/O The following I/O ports are routed from the backplane connectors to the rear panel connectors: • Ethernet (2x) •...
  • Page 124 Appendix E: Rear Transition module (RTM) Installing and configuring the RTM This explains how to install the EPC-3307 in a CompactPCI chassis. For information about... Go to this page... Inserting the RTM..................... 111 Removing the RTM................... 112 Inserting the RTM To insert the EPC-3307 RTM on the PCIbus backplane.
  • Page 125 EPC-3307 Hardware Reference Removing the RTM Occasionally you may need to remove the RTM to perform maintenance tasks such as replacing the battery. To remove the RTM from the CompactPCI chassis: 1. Press the latch part of the extractors inward until the extractor handle swings out and pivots freely.

  • Page 126: Figure E-1. Epc-3307 Rear Transition Module: Connectors

    Appendix E: Rear Transition module (RTM) Connectors This details the connectors used by the EPC-3307 RTM and gives the signal pinout of each connector. For information about... Go to this page... Connector locations..................113 Backplane J3....................114 Backplane J5....................115 Ethernet ......................
  • Page 127 EPC-3307 Hardware Reference Backplane J3 The J3 connector specified in CompactPCI is a female 2mm-pitch 6 column by 19 row right angle Hard Metric (HM) connector. The signals on this connector are proprietary and include the USB port, COM 1 and COM 2 ports, and PMC socket B I/O signals.
  • Page 128 Appendix E: Rear Transition module (RTM) Backplane J5 The back plane connector J5 routes both Ethernet channels, keyboard and mouse, secondary EIDE, and PMC socket A I/O signals to the CompactPCI backplane. The next table shows this connector’s pinout. Table E-3. Backplane connector J5 ~TM_PRNT PMCAIO64 PMCAIO63...
  • Page 129 EPC-3307 Hardware Reference COM 1 header Table E-5. H1 (COM 1) pin-out Signal Signal Carrier detect Data set ready Receive data Request to send Transmit data Clear to send Data terminal ready Ring indicator Signal ground No connect COM 2 The RS-232 serial port is a male DB-9 DTE.
  • Page 130 Keyboard clock Ground Mouse clock The EPC-3307 keyboard and mouse pins are opposite the laptop industry standard. This allows a keyboard to plug in directly without the pigtail. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 131 EPC-3307 Hardware Reference PIM (PMC I/O module) The PIM connector, located on the RTM’s rear panel, accepts a PIM that receives rear I/O from PMC site B, connector J24. The pinout has a one-to-one mapping from PMC site J24 to PIM J24.
  • Page 132 Appendix E: Rear Transition module (RTM) Table E-10. PIM connector pin-out: J24 Signal Signal PMC B J24-1 PMC B J24-2 PMC B J24-3 PMC B J24-4 PMC B J24-5 PMC B J24-6 PMC B J24-7 PMC B J24-8 PMC B J24-9 PMC B J24-10 PMC B J24-11 PMC B J24-12...
  • Page 133 EPC-3307 Hardware Reference The externally accessible USB (Universal Serial Bus) connector, located on the RTM’s rear panel, is a 4-pin single height connector defined as follows: Table E-11. USB connector pin-out Signal Mechanical solder lug Shield ground DATA– DATA+ Ground...

  • Page 134: Figure F-1. Installing A Pmc Module

    1. Remove the EPC-3307 from the CompactPCI chassis as described in Removing the EPC-3307 on page 10. 2. Remove and save the blank face plate from the PMC slot in the EPC-3307 face plate. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 135: Figure F-2. Separating A Pmc Module From The Main Board

    EPC-3307 on page 9. Disconnecting the PMC module If your EPC-3307 includes an optional PMC module, you must disassemble the board before performing maintenance or upgrades on the EPC-3307. To separate the PMC module and the main board: Figure F-2. Separating a PMC module from the main board 1.

  • Page 136: Figure G-1. Flash Chip Configuration

    ......130 Using jumpers to re-program the flash chip ............. 131 About the flash chip The EPC-3307 flash chip contains these major sections: • Boot block: A 16 KB, hardware-write-protected area Boot block that contains the Boot Block program. This program: ESCD •...

  • Page 137: Figure G-2. Flash Chip Re-Programming Coverage

    EPC-3307 Hardware Reference About re-programming the flash chip On rare occasions, part or all of the flash chip contents may require replacement. Use extreme caution when re-programming the flash chip. The Boot Block rarely changes and should not require re-programming.

  • Page 138: Figure G-3. Flash Chip Re-Programming Process Flow

    Appendix G: Re-programming the flash chip When re-programming the flash chip, follow this process. The rest of this chapter includes detailed instructions for each task: Re-programming the flash chip What part to BIOS re-program Boot Block Download Download Download biosrec.zip bbrec.zip fbdrec.zip Create a...
  • Page 139 Boot Block: Re-program only the Boot Block. You will perform this type of update rarely, if ever. If the Boot Block is corrupt and not executable, return the EPC-3307 to the factory for repair. For information about returning items to RadiSys, see the RadiSys web site.
  • Page 140 Re-programming the flash chip requires a Flash Boot diskette that contains both code to perform the task and data to place in the chip. To create the Flash Boot diskette: 1. Locate the appropriate file from the RadiSys web site and download it to your computer: •...
  • Page 141 EPC-3307 Hardware Reference Now that you have created a Flash Boot diskette, re-flash your system using the directions for the re-flash method you want to use: Method Page Using phlash.exe to re-program the flash chip Using BIOS configuration options to re-program the flash chip Using jumpers to re-program the flash chip Artisan Technology Group - Quality Instrumentation ...
  • Page 142 Do not install this jumper unless a Boot Block update is required. A BIOS boot block rarely changes and seldom, if ever, requires re-programming. A. Turn system power off, then remove the EPC-3307 from the CompactPCI chassis. B. Connect these pins:...
  • Page 143 Do not install this jumper unless a Boot Block update is required. A BIOS boot block rarely changes and seldom, if ever, requires re-programming. A. Turn system power off, then remove the EPC-3307 from the CompactPCI chassis. B. Connect these pins:...
  • Page 144 Appendix G: Re-programming the flash chip Using jumpers to re-program the flash chip 1. Install the force recovery jumper: A. Turn system power off, then remove the EPC-3307 from the CompactPCI chassis. B. Locate the BIOS configuration jumper block and connect the appropriate pins:...
  • Page 145 EPC-3307 Hardware Reference Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 146 Glossary A factor in measurement of a memory storage device’s operating speed. It is the Access Time amount of time required to perform a read operation. More specifically, it is the period of time between which the memory receives a read command signal and the time when the requested data becomes available to the system data bus.
  • Page 147 EPC-3307 Hardware Reference A process whereby an existing, uncorrupted BIOS image in the flash boot device is BIOS Update overwritten with a new image. Also referred to as a flash update. A binary digit. The process of starting a computer and loading the operating system from a powered Boot down state (cold boot) or after a computer reset (warm boot).
  • Page 148 Glossary (Cylinders/Heads/Sectors) A specification of disk drive operating parameters consisting of the number of disk cylinders, disk drive read/write heads, and disk sectors. The state of all user-changeable hardware and software settings as they are originally Default configured before any changes are made. (Disk Operating System) One or more programs which allow a computer to use a disk drive as an external storage device.
  • Page 149 EPC-3307 Hardware Reference (Field Programmable Gate Array) A large, general-purpose logic device that is FPGA programmed at power-up to perform specific logic functions. (Flash Boot Device) A flash memory device containing the computer’s BIOS. In the NY1210, a 1 MByte Intel 28F800B5 semiconductor flash memory containing the system and video BIOS images, the BIOS initializing code and the recovery code which allows self hosted reflashing.
  • Page 150 Glossary microprocessor to jump to a special program called the interrupt service routine. The microprocessor executes this special program, which normally involves servicing the interrupting device. When the interrupt service routine is completed, the microprocessor resumes execution of the program it was working on before the interruption occurred.
  • Page 151 EPC-3307 Hardware Reference (Phase-Locked Loop) A semiconductor device which functions as an electronic feedback control system to maintain a closely regulated output frequency from an unregulated input frequency. The typical PLL consists of an internal phase comparator or detector, a low pass filter, and a voltage controlled oscillator which function together to capture and lock onto an input frequency.
  • Page 152 Glossary RTC is typically receives power from a small battery to retain the current time of day when the computer is powered down. The process of replacing a BIOS image, in binary format, in the flash boot device. Reflashing An area typically inside the microprocessor where data, addresses, instruction codes, Register and information on the status on various microprocessor operations are stored.
  • Page 153 EPC-3307 Hardware Reference (Static Random Access Memory) A semiconductor RAM device in which the data SRAM remains permanently stored as long as power is applied, without the need for periodically rewriting the data into memory. A SIMM, the memory content of which is configured as two independent banks.
  • Page 154 Index N A B C D E F G H K L M N O P Q R S T U V W X Y Z 134. chipset, defined Numerics clock, TOD 32-bit I/O CMOS RAM 104. COM 1 116. COM2 connector 133.
  • Page 155 105. 135. EDO DRAMs, defined Hot Swap signals humidity 100. 117. EIDE connector, primary 121. electrostatic discharge, avoiding e-mail address, RadiSys I/O device configuration ESCD block I/O Map ESD, avoiding addresses 121. ESD, preventing DMA controller Ethernet Parallel I/O (LPT1) Port 104.
  • Page 156 138. random access, defined Primary Slave sub-menu shadow 111. printer, connecting 140. system, defined Memory Cache sub-menu memory map 126. RadiSys, contacting MFG jumper RAM, CMOS 127. minidos.sys 138. RAM, defined 111. modem, connecting 138. Random Access Memory (RAM), defined mouse 127.
  • Page 157 IDE, I/O map 134. BIOS, defined serial I/O (COM 2) port 136. flash, defined I/O map 126. URL, RadiSys serial I/O (COM 4) port URLs I/O Map Intel 104. serial port 120. USB connector shadowing 140.
  • Page 158 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...

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