A3 Assembly Adc Circuits; Adc Control Signals - HP 8560E Service Manual

A3 Assembly ADC Circuits

The ADC consists of a 12-bit DAC, 12-bit successive approximation
register (SAR), data multiplexers, and data latches. The ADC ASM
(algorithmic state machine) controls the ADC. Eight inputs are
controlled by the ADC MUX. These include a positive peak detector,
negative peak detector, sampled video, scan ramp, YTO error voltage,
FC MUX voltages, Cal Oscillator tune voltage, and offset lock error
voltage. A MUX on the A14 frequency control assembly selects which
voltage is sent to the ADC MUX on the FC MUX signal line.
During NORMAL detector mode sweeps, when noise is detected by the
rosenfell detector, the ADC ASM automatically switches between POS
PEAK and NEG PEAK.

ADC Control Signals

Refer to function blocks B and F of A3 Interface Assembly Schematic
Diagram (sheet 2 of 6) in the
Component Level Information
The ADC requires two signals from the A2 controller assembly:
HBADC_CLK0 and HBBKT_PULSE. HBBKT_PULSE is used only in
zero span. Use the following steps to verify the signals:
1. Disconnect W22 from A2J8.
2. If a 10 MHz TTL signal is absent on W22, refer to the 10 MHz
Reference (on the A15 RF assembly) troubleshooting procedure in
Chapter 11.
3. Set the HP 8560E/EC
4. Reconnect W22.
5. With an oscilloscope probe, monitor A3J401 pin 20.
6. If TTL pulses are absent, the A2 controller assembly is faulty. Refer
to Chapter 9. The presence of TTL pulses indicates a faulty A3
assembly.
7. Monitor A3J401 pin 23 (HBADC_CLK0). If a 1 MHz TTL clock
signal is present, HBADC_CLK0 is working properly.
8. If HBKT_PULSE or HBADC_CLK0 is missing, disconnect A3W1
from A2J2.
9. Monitor A2U5 pin 3 for HBKT_PULSE and A2U5 pin 7 for
HBADC_CLK0.
10.If HBADC_CLK0 is absent, troubleshoot the A2 controller assembly.
11.HBKT_PULSE is absent, refer to the information on troubleshooting
Chapter 7
HP 8560 E-Series Spectrum Analyzer
.
to zero.
SPAN
ADC/Interface Section

A3 Assembly ADC Circuits

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