HP 8560E Service Manual page 339

General Troubleshooting
Block Diagram Description
in 8560 EC-series instruments
Fast ADC
Fast ADC is a standard feature in all 8560EC instruments.When sweep
times <30 ms are selected, the spectrum analyzer digitizes video signals
with the fast ADC circuitry on the A2 controller board. The fast ADC
uses an 8-bit flash ADC that is sampled at a 12 MHz rate. Only POS
PEAK, NEG PEAK, and SAMPLE detector modes are available with
the fast ADC; NORMAL detector mode is not available. Pre-triggering
is possible with the fast ADC.
(8560 E-series only)
A16 Fast ADC
When option 007 is installed, and sweep times <30 ms are selected, the
spectrum analyzer digitizes video signals with the A16 fast ADC. The
fast ADC uses an 8-bit flash ADC that is sampled at a 12 MHz rate.
Only POS PEAK, NEG PEAK, and SAMPLE detector modes are
available with the fast ADC; NORMAL detector mode is not available.
Pre-triggering is possible with the fast ADC.
Log Expand/Video Functions
The A3 interface assembly performs log expand and offset functions.
The log expand/log offset amplifier provides a 2 dB/div log scale. When
the main ADC is used, the 5 dB/div scale is derived by multiplying the
digitized 10 dB/div trace data by two in the CPU. When the fast ADC is
used, the 5 dB/div scale is derived by amplifying the video signal by
two. The 1 dB/div scale is derived by either multiplying the 2 dB/div
trace data by two (main ADC) or amplifying the video signal by two
(fast ADC).
The spectrum analyzer uses two types of video filters. An RC low-pass
circuit provides 300 Hz to 3 MHz video bandwidths. Video bandwidths
of 1 Hz to 100 Hz are generated using digital filtering. When a digital
filter is selected, a D appears along the left edge of the CRT, indicating
that something other than the normal detector mode is being used.
Digitally filtered bandwidths use a sample detector.
After filtering, the video is sent to the positive and negative peak
detectors. These detectors are designed for optimum pulse response.
The positive peak detector resets at the end of each horizontal "bucket"
(there are 601 such buckets across the screen). The negative peak
detector resets at the end of every other bucket. When reset, the output
of the peak detector equals its input.
Triggering
The HP 8560E/EC has five trigger modes: free run, single, external,
video, and line. The free run and single trigger signal comes from the 1
MHz ADC clock. The line trigger signal comes from the A6 power
supply. Video triggering originates from the video filter buffer circuit on
A3. External triggering requires either a high or low TTL logic level as
determined by the setting of the trigger polarity function. The external
338 Chapter 6