Table of Contents
Advertisement
5.6.7. Connector X1100 ( Secondary IDE )
All signals are LVTTL compatible.
IDE_D0..15
IDE ATA Data Bus. These are the Data pins connected to Secondary Channel.
IDE_A0..2
IDE ATA Address Bus. These are the Address pins connected to Secondary Channel.
IDE_CS0#
IDE Chip Select 1 for Secondary Channel 0. This is the Chip Select 1 command output pin to enable the
Secondary IDE device to watch the Read/Write Command.
IDE_CS1#
IDE Chip Select 3 for Secondary Channel 1. This is the Chip Select 3 command output pin to enable the
Secondary IDE device to watch the Read/Write Command.
IDE_DRQ
IDE DMA Request for IDE Master. This is the input pin from the Channel IDE DMA request to do the
IDE Master Transfer. It will active high in DMA or Ultra-33 mode and always be inactive low in PIO
mode.
IDE_DACK#
IDE DACKJ for IDE Master. This is the output pin to grant the Channel IDE DMA request to begin the
IDE Master Transfer in DMA or Ultra-33 mode.
IDE_IORDY
IDE Ready. This is the input pin from the IDE Channel to indicate the IDE device is ready to terminate
the IDE command in PIO mode. The IDE device can de-assert this input (logic 0) to expand the IDE
command if the device is not ready. In Ultra-33 mode, this pin has different functions. In read cycle, IDE
device will drive this signal as Data Strobe (DSTROBE) to use by IDE Busmaster to strobe the input
data. In write cycles, this pin is used by IDE device to notify IDE Busmaster as DMA Ready
(DDMARDYJ).
IDE_IOR#
IDE IORJ Command. This is the IORJ command output pin to notify the IDE device to assert the Read
Data in PIO and DMA mode. In Ultra-33 mode, this pin has different function. In read cycle, this pin is
used by IDE Busmaster to notify IDE device as DMA Ready (DDMARDYJ). In write cycle, IDE
Busmaster will drive this signal as Data Strobe (DSTROBE) to use by IDE device to strobe the output
data.
IDE_IOW#
IDE IOWJ Command. This is the IOWJ command output pin to notify the IDE device that the available
Write Data is already asserted by IDE Busmaster in PIO and DMA mode. In Ultra-33 mode, this pin is
driven by IDE Busmaster to force IDE device to terminate current transaction. After receiving this input,
IDE device will de-assert DRQ to STOP current transaction.
DIAG_P
Output by the drive if it is jumpered in the slave mode; input to the drive if it is jumpered in the master
mode. The signal indicates to a master that the slave has passed its internal Diagnostic command.
Necessary for using IDE master/slave-mode on Secondary IDE channel.
IDE_SEL
IDE Cable select (470R to Ground)
Used to configure this device as a Master or a Slave. When the pin is grounded, this device is
configured as a Master. When the pin is open, this device is configured as a Slave.
IDE_RST#
Low active hardware reset (RSTDRV inverted).
IDE_IRQ
IDE channel interrupt signal.
Page 22 of 62 Pages
Advertisement
Table of Contents
