Printronix P6000 Series Maintenance Manual page 52

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2-6. Logic C3 PCBA
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continued
t. Address Bus
Three address busses exist on the C3 card: the unbuffered address bus, A1-A23, the buffered ad
dress bus BA1-BA23, and the memory address bus, MA0-MA7.
Devices on the unbuffered address bus include: the 68000 MPU the 68B44 DMA, the 12L10 PAL
and the 74ALS244 buffers. Devices on the buffered address bus include: the buffer outputs, the
rest of the decode logic (74LS138) and address selectable latches (74LS259) the EPROM, the
EEPROM and the DRAM memory address switching circuit.
The buffered memory address bus drives the DRAM addresses that are going to be accessed. The
three sources for DRAM addresses include the refresh circuit, the processor DRAM addresses,
and the hammer load circuit addresses.
u. Data Bus
There is one data bus on the card divided into two groups of eight: the upper and lower data byte.
The 68901 MFP resides on the lower data bus so the interrupt vector generated by the 68901 can be
read by the 68000. The 68B44 resides on the upper data bus for easier software access. 74ALS245
provide the bidirectional buffering of the data bus and are tri-stated when NBGACK (Bus Grant
Acknowledge) is asserted. The 74ALS245s are the only devices on the 68000 data bus pins.
v. Address Decoding
Extensive, but not complete address decoding is provided. The address decode circuit consists of a
12L10 PAL, several address selectable latches (74LS259), and several demultiplexors (74LS138).
The address decode, or memory map follows in Tables 2-8 and 2-9.
2-32 P6040/P6080 Principles of Operation