Printronix P6000 Series Maintenance Manual page 42

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Table 2-5. Microprocessor Bus Expansion Connector Pin Assignment
Pin Mnemonic
1A +5V
2A NADRDIS
3A IPL1(O)
4A IPL0(O)
5A BR/NW
6A BSN5
7A BSN1
8A BSN3
9A NBAS
10A BA7
11A BD15
12A BA6
13A BSN2
14A BD1
15A BD3
16A BD0
17A BA8
18A BA15
19A BD14
20A BA11
21A BD6
22A BA9
23A BA1
24A BA17
25A BA19
26A BA21
27A NMC
28A NBR(0)
29A NBG
30A BD5
31A NBGACK(O)
32A GND
NOTES:
1. (O) Denotes signal is open collector.
2. N Prefixing the signal name means active low.
3. All levels are TTL unless otherwise specified.
4. Segment lines are held in static states.
BSN6 is pulled high with 4.7K to +5V .
BSN1-BNSN5 all tied low to signal ground.
5. All data bus signals are buffered bidirectional.
6. All signals are outputs unless otherwise noted.
2-22
Description
Supply Voltage
CPU Address Disable
Interrupt Priority Level 1 to CPU
Interrupt Priority Level 0 to CPU
Buffered Read/Not Write
Segment Line #5
Segment Line #1
Segment Line #3
Buffered Address Strobe from CPU
Buffered Address Bus Line #7
Buffered Data Bus Line #15
Buffered Address Bus Line #6
Segment Line #2
Buffered Data Bus Line #1
Buffered Data Bus Line #3
Buffered Data Bus Line #0
Buffered Address Bus Line #8
Buffered Address Bus Line #15
Buffered Data Bus Line #14
Buffered Address Bus Line #11
Buffered Data Bus Line #6
Buffered Address Bus Line #9
Buffered Address Bus Line #1
Buffered Address Bus Line #17
Buffered Address Bus Line #19
Buffered Address Bus Line #21
Master Clear
Bus Request to CPU
Bus Grant from CPU
Buffered Data Bus Line #5
Bus Grant Acknowledge to CPU
Signal Ground
P6040/P6080 Principles of Operation
-continued