Adc Input Clock (Clk) Options; Figure 3-2. Clk Source (Schematic) - Texas Instruments ADS1285EVM-PDK User Manual

EVM Analog Interface

3.2 ADC Input Clock (CLK) Options

Using the onboard oscillator, clock dividers, and external connectors, the ADS1285EVM-PDK has device
configuration flexibility. The ADC operates from CLK, which generates the modulator clock (f
in one of two ways:
• A crystal oscillator and the accompanying clock dividers can provide a selectable frequency for the entire
range of the ADC.
– The onboard crystal oscillator (Y1) provides the nominal 8.192-MHz clock frequency (default)
– The dividers (U6) step down the frequency to 4.096 MHz
– J8 allows the user to select between these frequencies and connect them directly to CLK by using a shunt
• An external main clock can be provided to a subminiature version A (SMA) connector (J5) or to pins 4 or 2 of
J7 when a shunt does not select the frequency from the crystal oscillator.
– In this case, a shunt must not cover J7 so that CLK is connected to any of the crystal oscillator signals
– Be sure to review the valid CLKIN input frequency in the data sheet
All clock sources are sourced back to the PHI connector (J6) so that the GUI SCLK communication is
synchronous with CLK.
Figure 3-2 shows a schematic for the clock source.
DVDD
C21
0.1uF R30 Y1
100k
4
Vdd Output
GND
1
Tri-state Gnd
J8
2 ECS-2520MVLC-081.92-BN-TR
CLK DIS 1
On-board clock
Supply range: 1.71V - 3.63V
GND
8 ADS1285EVM-PDK Evaluation Module
3
2
2
CLK
GND
1 4
D Q
DVDD
5 3
VCC GND
C23
0.1uF U6
SN74AUP1G80DCKT
GND GND

Figure 3-2. CLK Source (Schematic)

Copyright © 2022 Texas Instruments Incorporated
Note
R29 49.9 DAC_4MHZ
8 MHz 3 4
4 MHz 1 2
J7
Connect jumper across to
select ADC clock frequency.
DNI if using FPGA clock.
SBAU394A – APRIL 2022 – REVISED SEPTEMBER 2022
www.ti.com
), provided
MOD
External clock
J5 CLK Options:
1 1) FPGA provides CLK output
2) External oscillator drives CLK (default)
R31
0
GND
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