Schematic Diagrams - NXP Semiconductors UJA1169A User Manual

NXP Semiconductors
4

Schematic diagrams

12 V
J2
1
SILK=12 V
2
SILK=GND
HDR_1X2
BAT
CON PWR 3
J6
D1
1 A C
3
PMEG3020EH
2
C1
100 µF
TP1 TP2
LED_GRN
SILK=BAT
BAT
R7
10 k
J1
PORT_CANL
2
SILK=L
PORT_CANH
1
SILK=H
HDR_1X2
1 2
SILK=CAN
D3
PESD1CAN
C5
3
51 pF
USER INTERFACE
J3
1
SILK=TXD
2
SILK=RXD
3
SILK=SDO
4
SILK=SDI
5
SILK=SCK
6 SCSN
SILK=SCSN
7
SILK=GND
8
SILK=V1
9 RSTN
SILK=RSTN
10
SILK=V2
11 WAKE
SILK=WAKE
12
SILK=GND
13
SILK=BAT
14
SILK=LIMP
HDR_1X14
(1) Component not populated.
Figure 16. UJA1169AF-EVB schematic diagram
UM11758
User manual
LAYOUT NOTE: PLACE R10, R13 CLOSE TO J9
J9
1 PNP_C
SILK=PNP_C
2 GND
SILK=GND
3 PNP_B
SILK=PNP_B
4
SILK=BAT
RHDR_1X4 (1)
R4
R1
1 k
C2
0.1 µF
D2
R5
10 k
LIMP_LED A
LED RED
R6 SILK=BAT
10 k
PB_WAKE
4 2
C7
SW1
0.01 µF
SW SPST TH
3 1
SILK = WAKE
2 1
L1
100 µH
4 3
R2 R3
62 62
CAN_T
(1) (1)
C6
51 pF
C4
4700 pF
TXD
RXD
SDO SCSN
SILK=SCSN
SDI SDI
SILK=SDI
SCK SDO
SILK=SDO
SCK
SILK=SCK
V1
SILK=GND
V2
BAT
LIMP
All information provided in this document is subject to legal disclaimers.
C9
LAYOUT NOTE: PLACE C9 CLOSE TO Q1
0.01 µF
3
2
PHPT61003PY
PNP_E
1 5
Q1
4
R15
100 k
R10
TP4
VEXCTRL
U1
15 6 V1
5
BAT
14
RST
8
D4
C
LIMP SCS
11 20
SDO
9
SDI
3
WAKE
12 SCK
10
TXD
2
CANL
17
RXD
CANH 7
18
V2
13
1 4 16 19 21
CANL
UJA1169ATK/F
CANH
ARDUINO INTERFACE
J4
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18 TXD
19 20
RXD
HDR_2X10
Rev. 1 — 19 April 2022
UJA1169A evaluation boards
R13
1.6
V1
R14
10 k
SCSN
SDO
SDI
SCK
TXD
RXD
V2
VIN
J5
16 15
SILK=VIN
14 13
12 11
10 9
8 7
RSTN
6 5
IOREF
4 3
2 1
SILK=VIN
SILK=TXD
HDR_2X8
SILK=RXD
J8
HDR_1X2
JUMPER (DEFAULT) = ON
UM11758
R9
D5
1 k
V1_LED
A C
C8
LED_GRN
6.8 µF
SILK=V1
RSTN
R8
D6
1 k
V2_LED
A C
C10
LED_GRN
6.8 µF
SILK=V2
SILK=GND
V1
SILK=RST
SILK=IOREF
J7
SILK=V1
12 V
HDR 1X2
JUMPER (DEFAULT) = ON
SILK=12 V
aaa-045591
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