Uja1169A With One Pnp - NXP Semiconductors UJA1169A User Manual

NXP Semiconductors

2.2.2.1 UJA1169A with one PNP

UM11758
User manual
all dynamic load changes within the package while the external PNP delivers additional
supply current to the application.
Detailed information on the functionality and operation of the UJA1169A can be found in
the data sheet and application hints (see
By default, all UJA1169Ax-EVB boards are delivered with an onboard PNP (e.g.
PHPT61003PY from Nexperia). A simplified circuit diagram is shown in
Shunt resistor R13 is used to limit the current delivered by the external PNP transistor
and to protect the PNP transistor against a V1 short-circuit to GND.
Pull-up resistor R15 is used to pull up the PNP base voltage to prevent it floating (e.g. if
R10 has been removed) and therefore ensure that the PNP is turned OFF.
Filter capacitor C9 is needed to protect V1 against an overvoltage during RF-injection on
the battery line. For EMI optimization, C9 is placed close to the PNP emitter.
R4 and R10 are provided to allow the PNP to be easily disconnected.
UJA1169A
Figure 3. Simplified schematic of UJA1169Ax-EVB with one PNP.
Figure 4. UJA1169Ax-EVB PCB configured to operate with one PNP.
All information provided in this document is subject to legal disclaimers.
Section
J3
VEXCTRL (p15)
VEXCC (p6)
V1 (p5)
V1
GND
(p1, 4, 16, 19)
GND
Rev. 1 — 19 April 2022
UJA1169A evaluation boards
7).
BAT
R4
0 Ω
C9
R15
10 nF
R10
100 k
0 Ω
PNP
R13
1.6 Ω
J7
C8
6.8 F
R9
1 k
D5
LED
UM11758
Figure 3.
BAT
J9
GND
PNP_B
PNP_C
VDD
J5
GND
aaa-045443
© NXP B.V. 2022. All rights reserved.
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