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UM11385
P3A9606JK-EVB evaluation board
Rev. 1.0 — 21 June 2020
Document information
Information
Content
Keywords
P3A9606JK, Level Shifter, Level Translator, P3A9606JK-EVB evaluation
board
Abstract
The P3A9606JK is a 2-bit, dual supply translating transceiver with auto
direction sensing that enables bidirectional voltage level translation. This user
manual describes the setup, configuration and operation of the P3A9606JK-
EVB evaluation board.
User manual
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Summary of Contents for NXP Semiconductors P3A9606JK-EVB
- Page 1 User manual Document information Information Content Keywords P3A9606JK, Level Shifter, Level Translator, P3A9606JK-EVB evaluation board Abstract The P3A9606JK is a 2-bit, dual supply translating transceiver with auto direction sensing that enables bidirectional voltage level translation. This user manual describes the setup, configuration and operation of the P3A9606JK-...
- Page 2 UM11385 NXP Semiconductors P3A9606JK-EVB evaluation board Revision history Date Description v.1.0 20210621 Initial version UM11385 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. User manual Rev. 1.0 — 21 June 2020...
- Page 3 UM11385 NXP Semiconductors P3A9606JK-EVB evaluation board Important notice NXP provides the enclosed product(s) under the following conditions: This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals.
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Page 4: Introduction
A1/A0 and B1/B0 of the P3A9606JK. External VCCA/VCCB can be manually selected and connected to the evaluation board. As default, P3A9606JK-EVB evaluation board is configured (with jumper settings) to be mated to a CERES motherboard serial expansion bus as a level shifter on the SPMI bus. -
Page 5: Connectors And Jumpers
Figure 1. Location of connectors and jumpers 3.3 Default jumper settings (CERES motherboard SPMI bus option) As default, P3A9606JK-EVB evaluation board is configured to be mated to a CERES motherboard serial expansion bus as a level shifter on the SPMI bus as shown in Table Table 1. Default jumper settings... -
Page 6: Non-Ceres Motherboard Jumper Settings
UM11385 NXP Semiconductors P3A9606JK-EVB evaluation board Table 1. Default jumper settings ...continued Header Jumper on Comment Open VCCA is supplied from external, J20 Open VCCB is supplied from external, J22 Open Not used, CERES motherboard is on port A1 Open Not used, CERES motherboard is on port B1... -
Page 7: Test Points
UM11385 NXP Semiconductors P3A9606JK-EVB evaluation board 3.6 Test points There are a number of test points to allow the user to monitor and observe signals coming in and out of P3A9606JK. Table 4. Test points Signal Test point Alternative test point... -
Page 8: Legal Information
5.1 Definitions and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this Draft —... - Page 9 UM11385 NXP Semiconductors P3A9606JK-EVB evaluation board Tables Tab. 1. Default jumper settings ........5 Tab. 4. Test points ............7 Tab. 2. Non-CERES motherboard jumper settings ..6 Tab. 5. Errata list ............7 Tab. 3. Bypass jumper settings ........6 Figures Fig.
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Page 10: Table Of Contents
UM11385 NXP Semiconductors P3A9606JK-EVB evaluation board Contents Introduction ............4 Finding kit resources and information on the NXP web site ..........4 Collaborate in the NXP community ....4 Getting to know the hardware ......4 Kit overview ............4 Connectors and jumpers ........5 Default jumper settings (CERES motherboard SPMI bus option) ......5...
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