Introduction; General Spi Interface - Renesas ForgeFPGA User Manual

ForgeFPGA Configuration Guide

3. Introduction

An internal Configuration Wrapper is used to configure the ForgeFPGA core. The configuration can be done
from three different configuration bitstream sources:
–
External SPI/QSPI Flash
–
Internal OTP
–
MCU as a host
The ForgeFPGA Designer Software is used to generate bitstreams. The schematic in
diagram of the SLG47910 configuration block and the external MCU Host and QSPI Flash interface. The four
Configuration pins are GPIO3 (SPI_CLK), GPIO4(SPI_SS, Chip Select), GPIO5(SPI_SI, serial input) and
GPIO6(SPI_SO, serial output). GPIO9 is used as a Config Done signal.
SPI Master and SPI Slave blocks during configuration.
MCU
Host
4
QSPI
SPI
Flash
otp_data_rd
Q
otp_ctrl
OTP
op_data_wr
D
Table 1: Configuration Modes
Configuration Mode
QSPI/SPI
MCU
READ OTP
Write OTP

4. General SPI Interface

A 4-wire SPI device has four signals (see
1. SCLK: Serial Clock (output from Master). When the master communicates with the slave, the data on MOSI
or MISO pin will be synchronized with the Serial Clock. In the SPI protocol, the master produces the clock. The
slave will only receive the clock, so the slave has no control over the serial clock, which is produced by the
master.
2. MOSI: Master-Out Slave-In (data output from master). MOSI is a data pin. This pin is used to transmit data
from the Master to the Slave device. Whenever the master sends data, that data will be collected over the MOSI
pin by the slave.
Rev.1.0
May 31, 2022
tx_data
SPI
tx_data
Master
ctrl
SPI tx_data
ctrl
Slave
ctrl
ctrl
OTP
Programmer
Figure 1: SLG47910 Programming Interface
SPI Block Activated
Master
Slave
Slave
Slave
Figure 2):
Table 1
Configuration Wrapper
Config Loader
Clock Source
FPGA
MCU
External to FPGA
External to FPGA
Figure 1 shows a block
shows which modes activate the
conf
FPGA Core
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