Writing The Otp Block - Renesas ForgeFPGA User Manual

ForgeFPGA Configuration Guide
6.1

Writing the OTP Block

The OTP is written using the SPI Slave interface. The OTP write starts with ramp up of the voltage signals
VDDC to 1.1 V and VDDIO to 2.9 V which sets the NVM into write program mode. There is an otp_controller that
sequences the internal signals to enable the OTP write.
Once the overdrive and program mode inputs are active, the otp_controller will decode the spi_slave data, and
give, data address and control information to the otp_write_controller block to initiate the OTP write.
shows the OTP Write Packet
indicated by setting Byte8 bit[6]. Reserve bits are indicated by R and the parity bit by P. After writing the OTP the
write data should be checked using the OTP read command. Once the SLG47910 OTP has been written and
after POR or bringing the PWR pin low, MCU, QSPI, OTP write, and OTP read will be disabled. The SLG47910
will only load program data from the OTP. This is a design security feature.
Writing to the OTP has the following steps:
1. Wait for POR and PLL lock time (1300 us), then send the Signature Bytes through SPI_MOSI (GPIO_5) by
keeping SPI_SS (GPIO_4) low.
2. After the Signature bytes match, GPIO_9 (Config-Sig match) goes high and giving delay of 80 us and then
sending the OTP write command packets with delay gap between 1st and 2nd packet is 18 us delay and
consecutive packets is 10.11us delay. (S13)
3. In the last write packet Byte8[6] =1 which indicates the last write.
4. When done writing OTP bring PWR =L which resets the device, then at S5 chk_otp_en will be one.
Rev.1.0
May 31, 2022
Figure 10: Power Sequencing through Different Modes
format. Table 4 shows the Write/Read options bits. The last Write packet is
Table 3
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