Renesas ForgeFPGA User Manual page 12

ForgeFPGA Configuration Guide
18 GPIO5
19 GPIO6
After the 10 us is up, the SPI Master sends a Fast Read Command with 24-Address on the SPI_SO pin and
receives the data on the SPI_SI port as shown (see
QSPI flash is the lowest byte of a 32-bit data word.
After transferring the required number of configuration data bits, the wrapper ends the Fast Read command by
de-asserting its SPI_SS select output. To conserve power, the wrapper then issues a final Deep Power-down
command, 0xB9.
Figure 14. SPI Read Fast Command & Deep Power-Down Command
The SLG47910 device configures using a single data pin SPI_SI.
The procedure to enable QSPI Configuration are given below:
1. Hold GPIO4 (SPI_SS) High for a minimum delay of 1055 us. To enable QSPI mode. (S9)
2. After entering QSPI mode, internal logic will release GPIO4 (SPI_SS) from driving through the GPIO. (S9)
3. The internal Config-Wrapper which acts as master will control the SPI interface (GPIO3, GPIO4, GPIO5 &
GPIO6) throughout the FPGA configuration. (S9 -> S11)
4. The wrapper sends a wake-up command (AB) to QSPI flash device first and then it sends fast read command
(QB). After the configuration completes it sends the sleep command (B9). (S9 -> S11)
5. Config wrapper will generate internal Config done = 1 (S16)
Rev.1.0
May 31, 2022
SPI_SI (MISO)
SPI_SO (MOSI)
Figure 13. SPI Release from Deep Power Down Command
Figure 14). The first data byte (Data Byte 0) read from the
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