System Overview - Renesas CLK-104a Manual

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual

1. System Overview

The CLK-104 board consists an RF-PLL device (8V19N491-24 or 8V19N882) and two RF-synthesizer devices
(2x 8V97003). RF-PLL device can take one of the following three reference clocks as inputs to its CLK0/nCLK0
and CLK1/nCLK1 (both are differential inputs):
■ 156.25MHz from Xilinx RFSoC (ZCU-1275) board through above-mentioned connector
■
An onboard 10MHz TCXO
■
An external clock connected to SMA connectors
The RF-PLL devices generate the following output clocks:
■
A differential output for RF-synthesizer #1
■
A differential output for RF-synthesizer #1
■
A differential output for RF-synthesizer #2
■
A differential output to a pair of onboard SMA connectors for monitoring
■
6 differential outputs connecting to ZCU-1275 board (through the connector)
A diagram of the CLK-104 board is displayed below.
The RF-PLL device and two RF-synthesizer devices are accessible by an SPI interface. As stated above, they
can be accessed by an I2C-to-SPI converter from/to the ZCU-1275 board. The I2C signals are within the mating
connector between the two boards. Please note that the SPI port has been connected to an onboard 5×2 header
by which an external SPI master can access all devices on CLK-104 board.
The CLK-104 board can be powered locally or by plugging it into the ZCU-1275. For more information, see
"Standalone Testing."
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Figure 2. CLK-104 Board Diagram
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