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Internal I/O Connectors
X
SMBus Connector
SYS FAN1 CPU FAN1
7
1
7
1
DDR4_3
USB 3/4
1
1
1
DP+
5
8
2
8
2
+12V Power
Front LAN
Front LAN
Battery
LED 1/2
LED 3/4
LAN 1/2
LGA 1200
DP/COM1
HDMI
VGA
LAN3
USB 1/2
(USB 3.1 Gen 1)
LAN4
USB 7/8
(USB 3.1 Gen 2)
M.2 M Key
Mic In
Line Out
Line In
Note
2280
2260
2242
DDR4_1
PCIE1 (PCIe x16)
Buzzer
PCIE2 (PCIe x16)
Intel
JP2
6
2
6
2
JP1
5
1
5
1
6
2
6
2
JP4
PCIE3 (PCIe x4)
JP3
JP14/13/12/11
W480E/Q470E
1
5
1
5
(right to left)
USB 3.2 Gen 2
1
(USB 5/6)
2
JP15
3
3
3
3
J12
3
1
10
2
1
PCIE4 (PCIe x4)
Front
9
10
1
1
1
1
1
5
20
11
Audio
JP10/8/6/7
USB 11/12
(left to right)
(USB 2.0)
Note
1
JP24
11
20
2
6
2
6
2
6
2
6
3
1
1
1
1
1
1
1
5
S/PDIF
1
5
1
5
1
5
10
1
1
10
2
10
2
Digital I/O (DIO)
USB 9/10 (USB 2.0)
SYS FAN3 SYS FAN2
DIO Power
JP5
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
User's Manual | CMS310
DDR4_4
14
13
2
1
LPC
12
24
ATX
power
Standby
Power
LED
1
13
1
2
Front
Panel
11
SPI Flash
BIOS
1
2
PS2
DDR4_2
9
5
1
„ SMBus
6
2
JP27
SATA0/1
(left/right)
5
SATA2/3
SMB_ALERT
(left/right)
CASE
SMB_DATA
SMB_CLK
9
1
2
1
OPEN
3
2
3V3DU
9
1
1
GND
M.2 E Key
2
JP26
2230
9
1
2
1
2
9
1
2
COM1/2/3/4
(top to bottom)
Internal I/O Connectors
X
LPC Connector
SYS FAN1 CPU FAN1
DDR4_3
7
1
7
1
USB 3/4
1
1
1
DP+
5
8
2
8
2
+12V Power
Front LAN
Front LAN
Battery
LED 1/2
LED 3/4
LAN 1/2
LGA 1200
DP/COM1
HDMI
VGA
LAN3
USB 1/2
(USB 3.1 Gen 1)
LAN4
USB 7/8
(USB 3.1 Gen 2)
M.2 M Key
Mic In
Line Out
Line In
Note
2280
2260
2242
DDR4_1
DDR4_2
PCIE1 (PCIe x16)
Buzzer
PCIE2 (PCIe x16)
Intel
JP2
JP1
6
2
6
2
5
1
5
1
6
2
6
2
PCIE3 (PCIe x4)
JP4
JP3
JP14/13/12/11
W480E/Q470E
5
1
5
1
(right to left)
USB 3.2 Gen 2
1
(USB 5/6)
2
JP15
3
3
3
3
J12
3
1
10
2
1
PCIE4 (PCIe x4)
Front
1
1
1
1
9
10
1
5
20
11
M.2 E Key
Audio
JP10/8/6/7
USB 11/12
(left to right)
2230
(USB 2.0)
Note
1
JP24
11
20
3
2
6
2
6
2
6
2
6
1
1
1
1
1
1
1
5
1
5
1
5
1
5
S/PDIF
10
1
1
10
2
10
2
Digital I/O (DIO)
SYS FAN3 SYS FAN2
USB 9/10 (USB 2.0)
DIO Power
JP5
The Low Pin Count Interface was defined by Intel
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
Pin
Assignment
1
CLK
3
RST#
5
FRAME#
7
LAD3
9
LAD2
11
SERIRQ
13
5V5B
Chapter 2
HARDWARE INSTALLATION
„ LPC Connector
14
13
DDR4_4
14
13
2
1
LPC
2
1
12
24
ATX
power
Standby
Power
LED
1
13
1
2
Front
Panel
11
SPI Flash
BIOS
1
2
PS2
5
1
9
6
2
JP27
SATA0/1
(left/right)
SATA2/3
(left/right)
CASE
9
2
1
1
OPEN
3
2
9
1
1
2
JP26
9
1
2
9
1
2
COM1/2/3/4
(top to bottom)
Corporation to facilitate the industry's transi-
®
Pin
Assignment
2
L_AD1
4
L_AD0
6
VCC3
8
GND
10
---
12
GND
14
5V
28
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