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Internal I/O Connectors
X
SMBus Connector
SYS FAN1 CPU FAN1
7
1
DDR4_3
1
1
VGA
1
HDMI
5
8
2
+12V Power
Front LAN
Battery
LED
LAN 1
USB3 1/2
LGA 1200
LAN 2
DP/COM1
USB3 3/4
HDMI
VGA
DP/COM1
LAN 3/4
HDMI
VGA
USB3 7/8
DP
M.2 M Key
Line Out
Mic In
2280
2260
2242
DDR4_1
1
J12
PCIE1 (PCIe x16)
Buzzer
6
PCIE2 (PCIe x1)
Intel
JP2
5
1
5
1
JP1
6
2
6
2
PCIE3 (PCIe x16)
5
1
5
1
JP4
JP3
W480E/Q470E
6
2
6
2
10
1
3
JP13/11
1
10
1
3
USB3 Gen2
PCIE4 (PCIe x4)
(up to down)
1
Front
(USB 5/6)
Audio
11
20
JP10/8
JP25
(left to right)
20
J1
20
4
1
J30
J22
1
3
2
6
2
6
11
11
1
10
1
10
1
S/PDIF
1
1
5
1
5
10
1
1
1
10
J2
JP5
USB2_11/12
USB2_13/14
USB3_9/10
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
SMBus (J12)
Pin
Assignment
1
3V3DU
3
SMB_CLK_RESUME
5
SMBALERT_PCH-
User's Manual | CMS311-W480E/Q470E
DDR4_4
14
13
2
1
LPC
12
24
ATX
power
Standby
Power
LED
1
13
1
2
Front
Panel
11
SPI Flash
BIOS
1
CN37
DDR4_2
3
JP26
1
SATA0/1
5
(left/right)
SMB_ALERT
SATA2/3
(left/right)
SMB_DATA
SMB_CLK
6
1
1
3V3DU
6
6
1
GND
JP7
JP6
JP24
9
1
2
1
1
SOJ2
9
1
1
2
COM1/2
(top to bottom)
Pin
Assignment
2
GND
SMB_DATA_
4
RESUME
6
--
Internal I/O Connectors
X
LPC Connector
SYS FAN1 CPU FAN1
7
1
DDR4_3
1
1
VGA
1
HDMI
5
8
2
+12V Power
Front LAN
Battery
LED
LAN 1
USB3 1/2
LGA 1200
LAN 2
DP/COM1
USB3 3/4
HDMI
VGA
DP/COM1
LAN 3/4
HDMI
VGA
USB3 7/8
DP
M.2 M Key
Line Out
Mic In
2280
2260
2242
DDR4_1
DDR4_2
1
J12
PCIE1 (PCIe x16)
Buzzer
6
PCIE2 (PCIe x1)
Intel
JP2
5
1
5
1
JP1
6
2
6
2
PCIE3 (PCIe x16)
5
1
5
1
JP4
JP3
W480E/Q470E
6
2
6
2
10
1
3
JP13/11
1
10
1
3
(up to down)
USB3 Gen2
1
Front
PCIE4 (PCIe x4)
JP7
(USB 5/6)
Audio
20
11
JP10/8
JP25
(left to right)
20
J1
20
1
J30
J22
4
1
1
11
3
2
6
2
6
11
1
10
1
10
1
S/PDIF
1
1
5
1
5
10
10
1
1
1
J2
JP5
USB2_11/12
USB2_13/14
USB3_9/10
The Low Pin Count Interface was defined by Intel
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
LPC (J21)
Pin
Assignment
1
CLK
3
RST#
5
FRAME#
7
LAD3
9
LAD2
11
SERIRQ
13
5VSB
Chapter 2
HARDWARE INSTALLATION
„ LPC Connector
14
13
DDR4_4
14
13
2
1
LPC
2
1
12
24
ATX
power
Standby
Power
LED
1
13
1
2
Front
Panel
11
SPI Flash
BIOS
1
CN37
3
JP26
1
SATA0/1
(left/right)
SATA2/3
(left/right)
6
1
1
6
6
1
JP6
JP24
9
1
SOJ2
9
1
1
2
COM1/2
(top to bottom)
Corporation to facilitate the industry's transi-
®
Pin
Assignment
2
LAD1
4
LAD0
6
VCC3
8
GND1
10
---
12
GND2
14
5V
27
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