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Internal I/O Connectors
X
SMBus Connector
JP4/2/3/1
(top to bottom)
SYS FAN1 CPU FAN1
DDR4_3
1
1
USB 7/8
2
6
1
(USB 2.0)
5
1
5
2
6
+12V Power
Battery
1
5
2
6
1
5
2
6
VGA
LGA 1200
1
5
HDMI
DP
LAN1
USB 1/2
(USB 3.2 Gen 2)
LAN2
USB 3/4
(USB 3.2 Gen 1)
USB 7/8/9/10
(USB 3.2 Gen 1)
M.2 M Key
Mic In
Line Out
Line In
Note
2280
2260
2242
DDR4_1
PCIE1 (PCIe x16)
PCI1
LAN LED
Intel
Buzzer
8
7
PCI2
USB 3.2 Gen1
2
1
(USB 5/6)
H420E/Q470E
1
1
10
J10
2
J12
PCIE2 (PCIe x4)
2
1
Front
9
10
1
5
20
11
Audio
USB 11/12
DIO Power
SYS FAN3
(USB 2.0)
Note
COM 6
19
1
3
3
3
9
1
1
1
1
1
S/PDIF
1
4
2
2
10
2
10
2
1
1
1
Digital I/O (DIO)
JP13/11/25
USB 9/10 (USB 2.0)
(left to right)
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
User's Manual | CMS330-Q470E/H420E
DDR4_4
9
1
J34
9
1
J35
2
14
13
9
1
J36
2
1
9
1
LPC
J37
12
24
ATX
power
Standby
Power
LED
1
13
1
2
Front
Panel
11
SYS FAN2
1
SPI Flash
BIOS
„ SMBus
DDR4_2
SATA0/1/2/3
(top to bottom)
1
3
5
JP5
HDDPWR
3
4
SMB_ALERT
JP26
1
1
SMB_DATA
SMB_CLK
JP24
1
2
3V3DU
SOJ2
5
6
GND
9
1
1
9
1
2
1
M.2 E Key
2230
9
1
9
1
2
COM2/3/4/5
(top to bottom)
Internal I/O Connectors
X
LPC Connector
JP4/2/3/1
SYS FAN1 CPU FAN1
(top to bottom)
DDR4_3
USB 7/8
1
1
2
6
1
(USB 2.0)
5
1
5
2
6
+12V Power
Battery
1
5
2
6
1
5
2
6
VGA
LGA 1200
1
5
HDMI
DP
LAN1
USB 1/2
(USB 3.2 Gen 2)
LAN2
USB 3/4
(USB 3.2 Gen 1)
USB 7/8/9/10
(USB 3.2 Gen 1)
M.2 M Key
Mic In
Line Out
Line In
Note
2280
2260
2242
DDR4_1
PCIE1 (PCIe x16)
PCI1
LAN LED
Intel
Buzzer
8
7
PCI2
USB 3.2 Gen1
2
1
(USB 5/6)
H420E/Q470E
1
1
10
J10
SOJ2
2
J12
PCIE2 (PCIe x4)
1
2
Front
9
10
20
11
Audio
1
5
USB 11/12
(USB 2.0)
DIO Power
SYS FAN3
Note
COM 6
19
1
3
3
3
9
1
1
1
1
1
S/PDIF
1
4
2
10
2
10
2
2
1
1
1
Digital I/O (DIO)
JP13/11/25
USB 9/10 (USB 2.0)
(left to right)
The Low Pin Count Interface was defined by Intel
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
Pin
Assignment
1
CLK
3
RST#
5
FRAME#
7
LAD3
9
LAD2
11
SERIRQ
13
5V5B
Chapter 2
HARDWARE INSTALLATION
„ LPC Connector
14
13
DDR4_4
9
1
J34
9
1
J35
2
14
13
9
1
2
1
J36
2
1
9
1
LPC
J37
12
24
ATX
power
Standby
Power
LED
1
13
1
2
Front
Panel
11
SYS FAN2
1
SPI Flash
BIOS
DDR4_2
SATA0/1/2/3
(top to bottom)
1
3
JP5
HDDPWR
3
4
JP26
1
1
JP24
1
2
5
6
9
1
1
9
1
M.2 E Key
2230
9
1
9
1
2
COM2/3/4/5
(top to bottom)
Corporation to facilitate the industry's transi-
®
Pin
Assignment
2
LAD1
4
LAD0
6
VCC3
8
GND
10
---
12
GND
14
5V
29
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