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Schematic, PCB Layout, and Bill of Materials
4.1 BOOSTXL-DAC-PORT Schematic
The EXT_LDAC is supplied to
the uC for SPI or I2C trigger. It
is also supplied to the DAC.
When EXT_LDAC is not
present, a timer is used to
Launchpad Interface
generate a synchronous LDAC
J13
1
3
5
SPI_BUF_EN
7
R41
33
9
EXT_LDAC
R42
33
11
13
15
17
19
ESQ-110-14-T-D
External Power Supply Interface
VCC
VSS
EXT_VDD
EXT_VIO
C15
C14
C13
C12
50V
50V
16V
16V
10uF
10uF
10uF
10uF
J12
1
GND
GND
GND
GND
2
3
4
5
393570005
EXT_VDD-max = 5.5V
GND
EXT_VIO-max = 3.6V
VCC-max = 43V
VSS-max = -21.5V
(VCC-VSS)-max = 43V
22
DAC53204EVM User's Guide
Launchpad Interface
3V3
5V
C1
10uF
10V
GND
1
2
3
4
5
6
7
8
R17
33
9
10
11
12
R11
33
13
14
15
16
R12
33
17
18
R13
33
19
20
J14
3V3
2
Push-pull IO Level Translator
C11
4
6
25V
8
R37
0.1uF
U2
10.0k
10
GND
R21
33
12
R45
33
1
VCCA
R39
33
GND
14
16
18
2
DIR
20
SCLK_A0
3
A1
R40
33
MOSI_CLR
4
A2
R44
33
CS0_A1
5
A3
SPI2C_USBBTC_RST
6
A4
LDAC
7
A5
8
A6
9
A7
10
A8
11
GND
12
GND
MISO_LDAC_RSTSEL
R38
0
SCL_USBBTC_RSTSEL_LDAC
SN74LVC8T245PW
R43
0
SDA_CLR_RSTSEL_LDAC
GND
For MSP430G2, the position of
MOSI and MISO are
interchanged. Hence, the resistor
options are provided
EXT_VDD
VDD
TP1
VDD
3
2
EXT_VIO
1
VIO
TP3
J9
3
VIO
2
5V
1
J10
VDD Selection
3V3
J11
VIO Selection
Figure 4-1. BOOSTXL-DAC-PORT Schematic Page 1
Copyright © 2021 Texas Instruments Incorporated
C2
10uF
10V
GND
GND
VIO
C6
C7
25V
25V
0.1uF
0.1uF
SPI_BUF_EN
24
R29
10.0k
VCCB
GND
GND
23
VCCB
22
OE
LDAC Low Jitter Path Selection
GND
21
R27
33
B1
BO_SCLK_A0
TP5
R28
33
20
B2
BO_MOSI_CLR
19
R26
33
B3
LDAC
BO_CS0_A1
18
R25
33
B4
BO_SPI2C_USBBTC_RST
17
R32
33
B5
16
B6
15
B7
14
B8
13
GND
GND
3V3
3V3
3V3
3V3
C5
25V
R22
R24
R23
0.1uF
U1
10.0k
10.0k
10.0k
1
VREF_A
GND
MISO_LDAC_RSTSEL
R20
33
2
A1
SCL_USBBTC_RSTSEL_LDAC
R19
33
3
A2
SDA_CLR_RSTSEL_LDAC
R18
33
4
A3
5
A4
LSF0204DPWR
DAC_VIO
TP4
DAC_VIO
SCL_USBBTC_RSTSEL_LDAC
R15
0
SDA_CLR_RSTSEL_LDAC
R14
0
External Power Supply Detection
R8
D1
CDBU0245
VDD
4.99k
R10
R7
D2
CDBU0245
VIO
1.0k
4.99k
R9
This circuit is mainly intended to
1.0k
check whether VDD and VIO
are in the recommended range or
GND
not.
GND
R35
33
BO_LDAC
EXT_LDAC
This jumper provides a clean
option to supply low-jitter
LDAC for high-THD
applications. When external
LDAC is not going through
J8
level translator, VIO must be at
3V3
VIO
C3
25V
0.1uF
14
VREF_B
GND
8
EN
GND
13
R6
33
B1
BO_MIS O_LDAC_RSTSEL
12
R5
33
BO_SCL_USBBTC_RSTSEL_LDAC
B2
BO_SCL_US BBTC_RSTSEL_LDAC
R4
33
BO_SDA_CLR_RSTSEL_LDAC
11
B3
BO_SDA_CLR_RSTSEL_LDAC
10
B4
R1
6
NC
VIO
9
10.0k
NC
R2
7
GND
10.0k
R3
DAC_VIO
GND
10.0k
BO_SCL_USBBTC_RSTSEL_LDAC
By default, DAC_VIO is OFF. However, the VIO is
BO_SDA_CLR_RSTSEL_LDAC
ON to make sure EEPROM is read. The VIO is by
default connected to 3V3 and then based on the
EEPROM reading, it is switch to the right value.
This assumes that the BO board has another buffer
to isolate the EEPROM signals from the DAC
unless DAC_VIO is present
SLAU851 – MARCH 2021
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