Renesas Single-Chip Microcomputer M306NKT3 User Manual page 84

M306NKT3-RPD-E User's Manual
(3) Timing Requirements
Table 4.7 and Figures 4.6 show timing requirements in memory expansion mode and microprocessor mode.
Table 4.7 Timing requirements
Symbol
tsu(DB-RD)
Data input setup time
tsu(RDY-BCLK) RDY# input setup time
tsu(HOLD-BCLK)
HOLD# input setup time
th(RD-DB)
Data input hold time
th(BCLK-RDY) RDY# input hold time
th(BCLK-HOLD)
HOLD# input hold time
td(BCLK-HLDA)
HLDA# output delay time
Common to "with wait" and "no wait" (actual MCU)
BCLK
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5 P5
0 -- 2
Common to "with wait" and "no wait" (this product)
BCLK
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5 P5
0 -- 2
* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.
Figure 4.6 Timing requirements
REJ10J0326-0400 Rev.4.00 Sep. 01, 2006
Item
tsu(HOLD-BCLK)
td(BCLK-HLDA)
tsu(HOLD-BCLK)
td(BCLK-HLDA)
Actual MCU
Min.
50
40
50
0
0
0
th(BCLK-HOLD)
td(BCLK-HLDA)
Hi-Z
th(BCLK-HOLD)
td(BCLK-HLDA)
Hi-Z
4. Hardware Specifications
This product
[ns] [ns]
Max. Min.
65
55
80
See left
See left
See left
40
Max.
See left
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