External Synchronous Dram (Sdram) - Renesas CPU Board M3A-HS19 User Manual

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2.3.3 External Synchronous DRAM (SDRAM)

The M3A-HS19 is provided with a 16-MB synchronous DRAM (SDRAM) as an external main memory. The SDRAM is
controlled by the SH7619 on-chip bus state controller. The SDRAM is accessed in 16-bit bus.
Table 2.3.3 lists SDRAM specifications used on the M3A-HS19, and Figure 2.3.3 shows its block diagram.
Items
Part Number
Configuration
Capacity
Access Time
CAS Latency
Refresh Interval
Row Address
Column Address
Number of Banks
SH7619(U1)
A14-13
A12-1
CS3#
CKIO
RD/WR#
RAS#
CAS#
DQMLU
DQMLL
D15-0
Rev.1.01 Oct 28, .2008
REJ10J1351-0101
Table 2.3.3 SDRAM Specifications
EDS1216AATA-75E
16 MB (16-bit bus width) x 1
16 MB
5.4 ns
2 (at 62.5 MHz bus clock)
4,096 refresh cycles in every 64 ms
A11- A0
A8 - A0
4-banks controlled by BA0, BA1
CKE
x 16
Figure 2.3.3 External SDRAM Block Diagram
Description
3.3V
2
11
16
Features and Specifications
2.3.3 External Synchronous DRAM
EDS1216AATA-75(U3)
(2 M x 16 bits x 4-bank)
BA1-0
A11-0
CS#
CLK
CKE
WE#
RAS#
CAS#
DQMU
DQML
DQ15-DQ0
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