Renesas CPU Board M3A-HS19 User Manual page 21

2
Table 2.3.2 Setting Example of Bus State Controller (Flash Memory Write and Read)
User Area
CS0 S29GL032A90TFIR4
<Write/Read Timing>
Write1
Th T1 Tw 1 Tw 2 Tw 3 Tw 4
CKIO
tWC tWC
tAD1
A21-A1
tCSD1
CS0#
RD#
tWED1
tCS
tAS tWP tWP
WE0#
tDS
tWDD1
D15-D0 DATA
Rev.1.01 Oct 28, .2008
REJ10J1351-0101
Applicable Device
Write2
Tw 5 T2 Tf Taw 1 Th T1 Tw 1 Tw 2 Tw 3
tAD1
tAD1
tCSD1
tCSD1
tWED1 tWED1
tCH
tAH
tWPH tWPH
tWDD1
tDH tWDH1 tDS
Figure 2.3.2 Flash Memory Read and Write Access Timing Example
2.3.2 Flash Memory S29GL032A90TFIR4 (Standard component)
Settings for Bus State Controller
CS0 Space Bus Control Register: CS0BCR
Initial value: H'36DB 0400 (MD3 = "L")
Recommended value: H'1000 0400
• Idle Cycles between Write-Read Cycles and
Write-Write Cycles
IWW[1:0] = B'01: 1 idle cycle inserted
• Data bus width
BSZ[1:0] = B'10: *Shall be ignored.
CS0 space wait control register: CS0WCR
Initial value: H'0000 0500
Recommended value: H'0000 0AC1
• Number of Delay Cycles from address, CS0#
Assertion to RD#, WEn#
SW[1:0] = B'01; 1.5 cycles
• Number of Access Wait Cycles
WR[3:0] = B'0101; 5 cycles
• Ignore external WAIT input
WM = B'1;
• Number of Delay Cycles from RD#, WEn# negation
to address, CS0# negation
HW[1:0] = B'01; 1.5 cycles
Tw 4 Tw 5 T2 Tf Taw 1 Th T1 Tw 1
tAD1
tAD1
tCSD1
tCSD1
tRSD
tWED1
tCH
tAH
tWP tWP tOEH
tDH tWDH1
DATA
Features and Specifications
Read1
Tw 2 Tw 3 Tw 4 Tw 5 T2 Tf
tAD1
tRC tRC
tCSD1
tRSD
ta(OE) tDF(CE)
ta(AD) tRDH1
ta(CE1) tRDS1 tDF(OE)
DATA
2-5