M3A-Hs19 Memory Mapping - Renesas CPU Board M3A-HS19 User Manual

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1.7 M3A-HS19 Memory Mapping

Area 0 bus width: (Default)
Data alignment: (SW4-1)
Figure 1.7.1 show the memory mapping examples of the SH7619 on the M3A-HS19.
Logical Address [31~29]
000~011
100~
101~
110~
111~
Address [28~0]
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1600 0000
H'1800 0000
H'1A00 0000
H'1C00 0000
H'1FFF FFFF
Note: H'0000 0000 to H'1FFF FFFF are the cache-enabled area.
Rev.1.01 Oct 28, 2008
REJ10J1351-0101
MD3 = 0
MD5 = 0(ON)
MD5 = 1(OFF)
Area
P0
P1
P2
P3
P4
(P0 and shadow area (P1, P2, P3))
Area MAP = 0
Flash Memory (4 MB)
Area 0 H'0000 0000~H'003F FFFF
64 MB
User Area
Reserved *
Area 1
(Do not use)
64 MB
Reserved *
Area 2
(Do not use)
64 MB
SDRAM (16 MB)
H'0C00 0000~H'0CFF FFFF
Area 3
64 MB
User Area
Area 4
User Area
64 MB
Reserved
Area 5A
(Do not use)
32 MB
Area 5B
User Area
32 MB
Reserved
Area 6A
(Do not use)
32 MB
Area 6B
User Area
32 MB
Reserved *
Area 7
(Do not use)
64 MB
Figure 1.7.1 SH7619 Memory Mapping Examples
•••16-bit
•••Big endian
•••Little endian
Cacheable/Non-cacheable
Cacheable
Cacheable
Non cacheable
Cacheable
Non-cacheable (on-chip I/O) etc.
Flash Memory (4 MB)
H'0000 0000~H'003F FFFF
H'0C00 0000~H'0CFF FFFF
Overview
1.7 M3A-HS19 Memory Mapping
MAP = 1
User Area
Reserved *
(Do not use)
Reserved *
(Do not use)
SDRAM (16 MB)
User Area
User Area
User Area
PCMCIA
User Area
PCMCIA
Reserved
(Do not use)
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