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KS86C6004/C6008/P6008 MICROCONTROLLERS (Preliminary Spec)
7
CLOCK CIRCUIT
MAIN OSCILLATOR LOGIC
To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator
circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the
CPU to efficiently process logic operations.
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:
— In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file
and current system register values are retained. Stop mode is released, and the oscillator started, by a reset
operation or by an external interrupt with RC-delay noise filter (for KS86C6004/C6008/P6008, INT0–INT2).
— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The
current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file
is retained. Idle mode is released by a reset or by an interrupt (external or internally-generated).
C1
X
6 MHz
C2
X
OUT
Figure 7-1. Main Oscillator Circuit
(Crystal/Ceramic Oscillator)
IN
KS86C6004
KS86C6008
CLOCK CIRCUIT
-1
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