Table of Contents
Advertisement
RESET and POWER-DOWN
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than
×
300
A. All system functions are halted when the clock "freezes", but data stored in the internal register file is
retained. Stop mode can be released in one of two ways: by a RESET signal or by an external interrupt.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal is released and returns to High level. All system and peripheral
control registers are then reset to their default values and the contents of all data registers are retained. A reset
operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'.
After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by
fetching the 16-bit address stored in ROM locations 0100H and 0101H.
Using an External Interrupt to Release Stop Mode
Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related
external interrupts cannot be used). External interrupts INT0–INT2 in the KS86C6004/C6008/P6008 interrupt
structure meet this criteria.
Note that when Stop mode is released by an external interrupt, the current values in system and peripheral
control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and
CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an
external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization
interval. To do this, you must make the appropriate control and clock settings before entering Stop mode.
The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service
routine, the instruction immediately following the one that initiated Stop mode is executed.
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select
peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt
logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.
There are two ways to release Idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and
CLKCON.4 are cleared to '00B'. If interrupts are masked, a reset is the only way to release Idle mode.
2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle
mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction
immediately following the one that initiated Idle mode is executed.
Only external interrupts that are not clock-related can be used to release Stop mode. To release Idle
mode, however, any type of interrupt (that is, internal or external) can be used.
8-2
KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec)
NOTE
Advertisement
Table of Contents
