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UNIVERSAL SERIAL BUS
INTERRUPT ENDPOINT STATUS REGISTER (EP1CSR)
EP1CSR is the control register for Endpoint 1, Interrupt Endpoint. This register is located at address F2H and is
read/write addressable.
Bit7
CLEAR_DATA_TOGGLE: MCU writes "1" to this bit to clear the data toggle sequence bit. When the
MCU writes a 1 to this register, the data toggle bit is initialized to DATA0.
Bit6–3 MAXP: These bits indicate the maximum packet size for IN endpoint, and needs to be updated by MCU
before it sets IN_PKT_RDY. Once set, the contents are valid till MCU re-writes them.
Bit2
FLUSH_FIFO: When MCU writes "1" to this register, the FIFO is flushed, and IN_PKT_RDY cleared.
The MCU should wait for IN_PKT_RDY to be cleared for the flush to take place.
Bit1
FORCE_STALL: MCU writes "1" to this register to issue a STALL Handshake to USB. MCU clears this
bit, to end the STALL condition.
Bit0
IN_PKT_RDY: MCU sets this bit, after writing a packet of data into Endpoint 1 FIFO. USB clears this bit,
once the packet has been successfully sent to the Host. An interrupt is generated when USB clears this
bit, so MCU can load the next packet.
MSB
CLEAR_DATA_TOGGLE
CONTROL ENDPOINT BYTE COUNT REGISTER (EP0BCNT)
EP0BCNT register has the number of valid bytes in Endpoint 0 FIFO. It is located at address F3H and is
read/write addressable. Once the MCU receives a OUT_PKT_RDY (Bit0 of EP0CSR) for Endpoint 0, then it can
read this register to find out the number of bytes to be read from Endpoint 0 FIFO.
11-6
Control Endpoint Status Register (EP1CSR)
.7
.6
.5
MAXP
Figure 11-4. Interrupt Endpoint Status Register (EP1CSR)
KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec)
F2H, R/W
.4
.3
.2
FLUSH_FIFO
.1
.0
LSB
IN_PKT_RDY
FORCE_STALL
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