Spi Interface; External Connections - VersaLogic EBX-22 Reference Manual

SPI Interface

The serial peripheral interface (SPI) can function in two modes on the EBX-22. In legacy mode,
the interface functions as implemented in other VersaLogic SBCs, such as the EBX-11 Rev. 6.00
and above, and makes use of a set of control and data registers. In "bit bang" mode, you can
operate the SPIBB register (1D7h) directly. Each mode is described in this section.
SPI is, in its simplest form, a three wire serial bus. One signal is a Clock, driven only by the
permanent Master device on-board. The others are Data In and Data Out with respect to the
Master. The VersaLogic SPI implementation adds additional features, such as chip selects and an
interrupt input to the Master. The Master device initiates all SPI transactions. A slave device
responds when its Chip Select is asserted and it receives Clock pulses from the Master.
The SPI clock rate can be software configured to operate at speeds between 1 MHz and 8 MHz.
Please note that since this clock is divided from a 33 MHz PCI clock, the actual generated
frequencies are not discrete integer MHz frequencies. All four common SPI modes are supported
through the use of clock polarity and clock idle state controls.
E C
XTERNAL ONNECTIONS
Up to four serial peripheral interface (SPI) devices can be attached to the EBX-22 at connector
J25 using the CBR-1401 or CBR-1402 cable. The interface provides the standard SPI signals:
SCLK (Serial Clock), MISO (Master In Slave Out), and MOSI (Master Out Slave In), as well as
four chip selects, SS0# to SS3#, and an Interrupt Input, SINT#.
EBX-22 Reference Manual
Table 30: SPI Expansion Bus Pinout
Signal
J25 Pin Name Function
1 V5_0 +5.0V (Protected)
2 SCLK Serial Clock
3 GND Ground
4 MISO Serial Data In
5 GND Ground
6 MOSI Serial Data Out
7 GND Ground
8 SS0# Chip Select 0
9 SS1# Chip Select 1
10 SS2# Chip Select 2
11 SS3# Chip Select 3
12 GND Ground
13 SINT# Interrupt Input
14 V5_0 +5.0V (Protected)
Interfaces and Connectors
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