Table of Contents
Advertisement
more information about this subject, refer to Section 6 of the LVDS Owner's Manual available from
National Semiconductor (http://www.national.com).
8.1.2 Display Timing Configuration
The graphic controller needs to be configured to match the timing parameters of the attached flat
panel display. To properly configure the controller, there needs to be some method to determine the
display parameters. Different module vendors provide differing ways to access display timing
parameters. Some vendors store the data in non-volatile memory with the BIOS setup screen as the
method for entering the data, other vendors might use a module or carrier based EEPROM. Some
vendors might hard code the information into the BIOS, and other vendors might support panel
located timing via the signals LVDS_I2C_CK and LVDS_I2C_DAT with an EEPROM strapped to 1010
000x. Regardless of the method used to store the panel timing parameters, the video BIOS will need to
have the ability to access and decode the parameters. Given the number of variables it is
recommended that carrier designers contact module suppliers to determine the recommend method
to store and retrieve the display timing parameters.
The Video Electronics Standards Association (VESA) recently released DisplayID, a second-generation
display identification standard that replaces EDID and other proprietary methods for storing flat panel
timing data. DisplayID defines a data structure that contains information such as display model,
identification information, colorimetry, feature support, and supported timings and formats. The
DisplayID data allows the video controller to be configured for optimal support for the attached display
without user intervention. The basic data structure is a variable length block up to 256 bytes with
additional 256 byte extensions as required. The DisplayID data is typically stored in a serial EPROM
connected to the LVDS_I2C bus. The EPROM can reside on the display or carrier. DisplayID is not
backwards compatible with EDID. Contact VESA (www.vesa.org) for more information.
8.1.3 Backlight Control
Backlight inverters are either voltage, PWM or resistor-controlled. The COM Express Specification
provides two methods for controlling the brightness. One method is to use the backlight control and
enable signals from the CPU chipset. These signals are brought on COM Express LVDS_BKLT_EN and
LVDS_BKLT_CTRL. LVDS_BKLT_CTRL is a pulse width modulated (PWM) output that can be connected
to display inverters that accept a PWM input. The second method it to use the LVDS I2C bus to control
an I2C DAC. The output of the DAC can be used to support voltage-controlled inverters. The DAC can
be used driving the backlight voltage control input pin of the inverter. The reference design shown in
Figure 15 supports this. A header is used to allow the user to configure the type of backlight inverter
signal used. In the example, a DAC from Maxim is used (MAX5362 http://www.maxim.com).
COM Express Carrier Type 2
Design Guide
Page 47 of 103
Advertisement
Table of Contents
