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PEG_RX10+
C85
PEG_RX10-
C86
PEG_TX10+
D85
PEG_TX10-
D86
PEG_RX11+
C88
PEG_RX11-
C89
PEG_TX11+
D88
PEG_TX11-
D89
PEG_RX12+
C91
PEG_RX12-
C92
PEG_TX12+
D91
PEG_TX12-
D92
PEG_RX13+
C94
PEG_RX13-
C95
PEG_TX13+
D94
PEG_TX13-
D95
PEG_RX14+
C98
PEG_RX14-
C99
PEG_TX14+
D98
PEG_TX14-
D99
PEG_RX15+
C101
PEG_RX15-
C102
PEG_TX15+
D101
PEG_TX15-
D102
SDVO_12C_CLK
D73
SDVO_I2C_DATA
C73
PEG_LANE_RV#
D54
PEG_ENABLE#
D97
COM Express Carrier Type 2
Design Guide
PEG Channel 10, Receive
Input Differential Pair
PEG Channel 10, Transmit
Output Differential Pair
PEG Channel 11, Receive
Input Differential Pair
PEG Channel 11, Transmit
Output Differential Pair
PEG Channel 12, Receive
Input Differential Pair
PEG Channel 12, Transmit
Output Differential Pair
PEG Channel 13, Receive
Input Differential Pair
PEG Channel 13, Transmit
Output Differential Pair
PEG Channel 14, Receive
Input Differential Pair
PEG Channel 14, Transmit
Output Differential Pair
PEG Channel 15, Receive
Input Differential Pair
PEG Channel 15, Transmit
Output Differential Pair
I2C based control signal
(clock) for SDVO device
I2C based control signal
(data) for SDVO device
PCI Express graphics lane
reversal input strap. pull low
on the carrier board to
reverse lane order
PEG enable function. strap
to enable PCI Express x16
external graphics interface.
Pull low to disable internal
graphics and enable the x16
interface.
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
O 2.5V
SDVO enabled if this line
CMOS
is pulled up to 2.5 V on
carrier board or on ADD2
I/O 2.5V
SDVO enabled if this line
OD CMOS
is pulled up to 2.5 V on
carrier board or on ADD2
I 3.3V
CMOS
I 3.3V
CMOS
Page 31 of 103
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