Emerson COM Express Carrier Design Manual page 19

PCIE_TX0+ A68
PCIE_TX0- A69
PCIE_RX1+ B64
PCIE_RX1- B65
PCIE_TX1+ A64
PCIE_TX1- A65
PCIE_RX2+ B61
PCIE_RX2- B62
PCIE_TX2+ A61
PCIE_TX2- A62
PCIE_RX3+ B58
PCIE_RX3- B59
PCIE_TX3+ A58
PCIE_TX3- A59
PCIE_RX4+ B55
PCIE_RX4- B56
PCIE_TX4+ A55
PCIE_TX4- A56
PCIE_RX5+ B52
PCIE_RX5- B53
PCIE_TX5+ A52
PCIE_TX5- A53
PCI_CLK_REF+ A88
PCIE_CLK_REF- A89
EXCD0_CPPE# A49
EXCD0_PERST# A48
EXCD1_CPPE# B48
EXCD1_PERST# B47
CB_RESET# B50
COM Express Carrier Type 2
Design Guide
PCIe channel 0. Transmit
Output differential pair.
PCIe channel 1. Receive Input
differential pair.
PCIe channel 1. Transmit
Output differential pair.
PCIe channel 2. Receive Input
differential pair.
PCIe channel 2. Transmit
Output differential pair.
PCIe channel 3. Receive Input
differential pair.
PCIe channel 3. Transmit
Output differential pair.
PCIe channel 4. Receive Input
differential pair.
PCIe channel 4. Transmit
Output differential pair.
PCIe channel 5. Receive Input
differential pair.
PCIe channel 4. Transmit
Output differential pair.
PCIe reference clock for all COM
Express PCIe lanes, and for PEG
lanes.
PCI ExpressCard0: PCI Express
capable card request, active
low, one per card
PCI ExpressCard0: reset, active
low, one per card
PCI ExpressCard1: PCI Express
capable card request, active
low, one per card
PCI ExpressCard1: reset, active
low, one per card
Reset output from module to
carrier board. Active low. Issued
by module chipset and may
result from a low SYS_RESET#
input, a low PWR_OK input, a
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
O PCIE COM Express only
allocates a single ref
clock
I CMOS
O CMOS
I CMOS
O CMOS
O CMOS
Suspend
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