Figure 21 Pci Clock Buffer Circuitry; Figure 22 Pci Device Down Example (Dual Uart) - Emerson COM Express Carrier Design Manual

Figure 20 PCI Clock Buffer Circuitry
In accordance with PCI Local Bus Specification, Revision 2.3, the PCI clock signal requires a rise and
fall time (slew rate) within 1 V/ns and 4 V/ns. The slew rate must be met across the minimum
peak-to-peak portion of the clock waveform, which is between 0.66 V and 1.98 V for 3.3 V clock
signaling. These parameters are very critical for EMI and must be observed during carrier board
layout when implementing the PCI Bus.
Figure 21 PCI Device Down Example (Dual UART)
COM Express Carrier Type 2
Design Guide
Page 63 of 103