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PCIE_CLK_REF+
A88
PCIE_CLK_REF-
A89
4.1 PCIe Graphics (PEG) Configuration
4.1.1 Using as External Graphic Card
To use the COM Express PEG lanes for an external graphics device or card, the module PEG_ENABLE#
line (pin D97 on the module C-D connector) must be pulled low. Pulling this pin low disables the
module's internal graphics controller and makes the PEG x16 interface available to an external
controller.
The usual effect of pulling PEG_ENABLE# low is to disable the on-module graphics engine. For some
modules, it is possible to configure the module such that the internal graphics engine remains active,
even when the external PEG interface is being used for a carrier board graphics device. This is module
dependent.
If the external graphics controller on the carrier board is down, then the PEG_ENABLE# line should be
pulled to GND on the carrier board.
4.1.2 Using as SDVO
The COM Express module graphics controller configures the PEG lines for SDVO operation if it detects
that COM Express signals SDVO_I2C_CLK and SDVO_I2C_DATA are pulled high to 2.5V, and if the
PEG_ENABLE# line is left floating. This combination leaves the module's internal graphics engine
enabled but converts the output format to SDVO. The SDVO_I2C_CLK and SDVO_I2C_DATA lines are
pulled to 2.5V on an ADD2 card.
For a device down SDVO converter, the SDVO_I2C_CLK and SDVO_I2C_DATA lines have to be pulled
up to 2.5V on the carrier board.
4.1.3 Using as General PCI Express Lanes
The COM Express PEG lanes may be used for general-purpose use if the PEG port is not being used as an
interface to an external graphics device. The characteristics of this usage are module and chipset
dependent.
Modules that employ desktop and mobile chipsets with PEG capability can usually be set up to allow
the COM Express PEG lanes to be configured as a single general purpose PCIe link, with link width
possibilities of x1, x4, x8 or x16. The x1 configuration should always work; the wider links may be
module and chipset dependent. Check with your vendor. Modules based on server-class chipsets may
allow multiple links over the PEG lanes–for example, an x8 link on COM Express PCIe lanes 16 through
23 and an x4 link over lanes 24 through 27. This is module and chipset dependent.
PEG_ENABLE# should be left open when the PEG lanes are to be used for general purpose PCIe links.
Page 32 of 103
PCIe reference clock for all
COM Express PCIe lanes and
for PEG lanes
O CMOS
COM Express only
allocates a single
reference clock
COM Express Carrier Type 2
Design Guide
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