Figure 2 Pci Express Clock Reference Schematic - Emerson COM Express Carrier Design Manual

If the carrier board implements only one PCIe device or slot, then the PCIe reference clock pair from the
module may be routed directly to that device or slot. However, if there are two or more PCIe devices or
slots on the carrier board, then the module's PCIe reference clock should be buffered using a PLL-based
zero-delay buffer. Such devices are available from IDT, Cypress Semiconductor, and others. The IDT
ICS9DB102, ICS9DB104 and ICS9DB106 have two, four, and six differential output replicas of the input
clock, respectively. The Cypress CY28401 provides eight copies of the differential input clock. Each
target device (PCIe device down chip, slot, ExpressCard slot, PEG slot) should get an individual copy of
the reference clock. The reference clock pairs should be routed as directly as possible from source to
destination.

Figure 2 PCI Express Clock Reference Schematic

The following notes apply to this figure:
 Nets that tie directly to the COM Express connector are indicated with the CEX flag in the off-page
connection symbol.
 Each clock pair is routed point-to-point to each connector or end device using differential signal
routing rules.
 Each clock output pair in the example shown is terminated close to the ICS9DB102 buffer pins with a
series resistor (shown as 33 ohms) and a termination to GND (shown as 49.9 ohms), per the
vendor's recommendation. Other vendors may have different recommendations, particularly in
regard to the source termination to GND.
 SMBUS software can enable or disable clock-buffer outputs. Disable unused outputs to reduce
emissions.
 The CLKREQ0# and CLKREQ1# should be pulled low to enable the corresponding clock buffer
outputs. For applications in which power management is not a concern, these inputs may be tied
low to permanently enable the outputs.
COM Express Carrier Type 2
Design Guide
Page 21 of 103