Emerson COM Express Carrier Design Manual page 8

21.1.1 Four-Layer Stack-up ............................................................................................... 91
21.1.2 Six-Layer Stack-up.................................................................................................. 91
21.1.3 Eight-Layer Stack-up .............................................................................................. 92
21.2 Trace-Impedance Considerations...................................................92
21.3 Routing Rules for High-Speed Differential Interfaces ......................94
21.3.1 PCI Express 1.1 Trace Routing Guidelines ............................................................... 96
21.3.2 USB Trace Routing Guidelines ................................................................................ 97
21.3.3 PEG 1.1 Trace Routing Guidelines........................................................................... 97
21.3.4 SDVO Trace Routing Guidelines ............................................................................. 98
21.3.5 LAN Trace Routing Guidelines ................................................................................ 99
21.3.6 Serial ATA Trace Routing Guidelines ..................................................................... 100
21.3.7 LVDS Trace Routing Guidelines ............................................................................ 101
21.4 Routing Rules for Single-Ended Interfaces .................................... 101
21.4.1 PCI Trace Routing Guidelines................................................................................ 102
21.4.2 IDE Trace Routing Guidelines ............................................................................... 103
21.4.3 LPC Trace Routing Guidelines............................................................................... 103
Page 8 of 103 COM Express Carrier Type 2
Design Guide