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12 LPC
The low pin count Interface was defined by Intel Corporation to facilitate the industry's transition
toward legacy free systems. It is a versatile, easy-to-use bus that can support low-bandwidth
peripherals such as serial ports, firmware memory, legacy peripherals and general-purpose inputs and
outputs. The LPC bus uses four data bits and a 33 MHz clock, yielding a maximum bandwidth of
approximately 16 MBps–about double the bandwidth of the legacy ISA bus.
It does not support legacy functionality on the module, such as PS/2 keyboard/mouse, serial ports, and
parallel ports since COM Express is designed to be a legacy free standard for embedded modules.
Instead, it provides an LPC interface that can be used to add peripheral devices to the carrier board
design. COM Express also provides interface pins necessary for (optional) carrier board resident PS
keyboard controllers.
12.1 LPC Signals Definition
Table 16 LPC Interface Signal
Implementing external LPC devices on the COM Express carrier board always requires customization of
the COM Express module's BIOS in order to support basic initialization for those LPC devices. Otherwise
the functionality of the LPC devices will not be supported by a plug and play or ACPI-capable system.
12.2 Reference Schematic
12.2.1 FWH Schematic
An example of a carrier board firmware hub (FWH) implementation is shown in Figure 23. Use the FWH
to store and execute BIOS code. A feature of the COM Express specification is the inclusion of the
BIOS_DISABLE# pin. If this pin is pulled low on the carrier board, then the BIOS on the module is
disabled. The BIOS can instead reside on the carrier board LPC or PCI buses. This is useful in some
regulatory situations in which it is required that regulatory technicians remove the BIOS, check its
Page 66 of 103
COM Express Carrier Type 2
Design Guide
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