Pcie Graphics (Pcie 16-31) And Sdvo; Table 4 Peg Signal Description - Emerson COM Express Carrier Design Manual

4 PCIe Graphics (PCIe 16—31) and SDVO
The COM Express PCIe Graphics (PEG) port is comprised of COM Express PCIe lanes 16—32. The primary
use of this set of signals is to interface to off-module graphics controllers or cards.
The COM Express Specification also allows these pins to be shared with a set of module-generated
SDVO lines.
If the PEG interface is not used for an external graphics card or SDVO, it may be possible to use these
PCIe lanes for other carrier board PCIe devices. The details of this usage are module and module
chipset dependent. Operation in an x1 link is also supported. Wider links (x2, x4, x8, x16) are chipset
dependent. For more details, see the corresponding COM Express module user's manual.
The COM Express Specification defines a fill order for this set of PCIe lanes. Larger link widths go to the
lower lanes. For more details, see the COM Express Specification.
These PCIE lanes support polarity inversion and lane reversal to make it convenient for routing.
To activate the lane reversal mode for the PEG port, the COM Express Specification defines an active
low signal PEG_LANE_RV#, which can be found on the module's connector at row D, pin D54. This pin
is strapped low on the carrier board to invoke lane reversal mode.
Check the specified module if it supports SDVO lane reversal.

Table 4 PEG Signal Description

Signal Pin
PEG_RX0+ C52
PEG_RX0- C53
PEG_TX0+ D52
PEG_TX0- D53
PEG_RX1+ C55
PEG_RX1- C56
PEG_TX1+ D55
PEG_TX1- D56
PEG_RX2+ C58
PEG_RX2- C59
PEG_TX2+ D58
COM Express Carrier Type 2
Design Guide
Description
PEG Channel 0, Receive
Input Differential Pair
PEG Channel 0, Transmit
Output Differentail Pair
PEG Channel 1, Receive
Input Differential Pair
PEG Channel 1, Transmit
Output Differential Pair
PEG Channel 2, Receive
Input Differential Pair
PEG Channel 2, Transmit
I/O Comment
I PCIE Shared with:
SDVO_TVCLKIN+
SDVO_TVCLKIN-
O PCIE Shared with:
SDVOB_RED+
SDVOB_RED-
I PCIE Shared with:
SDVOB_INT+
SDVOB_INT-
O PCIE Shared with:
SDVOB_GRN+
SDVOB_GRN-
I PCIE Shared with:
SDVOB_FLDSTALL+
SDVOB_ FLDSTALL-
O PCIE Shared with:
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