Emerson COM Express Carrier Design Manual page 60

PCI_AD31 C48
PCI_C/BE0# D26
PCI_C/BE1# C33
PCI_C/BE2# C38
PCI_C/BE3# C44
PCI_DEVSEL# C36
PCI_Frame# D36
PCI_IRDY# C37
PCI_TRDY# D35
PCI_STOP# D34
PCI_PAR D32
PCI_PERR# C34
PCI_REQ0# C22
PCI_REQ1# C19
PCI_REQ2# C17
PCI_REQ3# D20
PCI_GNT0# C20
PCI_GNT1# C18
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PCI bus multiplexed
address and data lines
PCI bus byte enable line 0,
active low
PCI bus byte enable line 0,
active low
PCI bus byte enable line 0,
active low
PCI bus byte enable line 0,
active low
PCI bus Device Select,
active low
PCI bus Frame control
line, active low
PCI bus Initiator Ready
control line, active low
PCI bus Target Ready
control line, active low
PCI bus STOP control line,
active low
PCI bus parity
Parity error; an external
PCI device drivers PERR#
by driving it low, when it
receives data that has a
parity error
PCI bus master request
input line, active low
PCI bus master request
input line, active low
PCI bus master request
input line, active low
PCI bus master request
input line, active low
PCI bus master grant
output line, active low
PCI bus master grant
output line, active low
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I 3.3V
I 3.3V
I 3.3V
I 3.3V
O 3.3V
O 3.3V
COM Express Carrier Type 2
Design Guide