Digital I/O Definition; Configuration Sequence; Function Call Reference - Advantech ITA-3650G Series User Manual

6.1

Digital I/O Definition

See Chapter 2.4.
6.2

Configuration Sequence

The ITA-3650G's onboard GPIO with LPC bus is realized by Lattice CPLD.
The CPLD GPIO IC is configured and accessed via IO space accessing the system.
Mapping between GPIO IO Space and corresponding GPIO pins:
Port GPO: IO 0xC10~0xC12 (bit0-bit23)
Port GPI: IO 0xC13~0xC15 (bit0-bit23)
Note! ITA-3650G uses 48 bit CPLD for GPIO control, 24 GPI and 24 GPO
totally.
If a GPIO pin is set as input, users can read the corresponding input value from a bit
of the IO Space register.
If a GPIO pin is set as output, users can read the corresponding output value from a
bit of the IO Space register.
6.3

Function Call Reference

GPIO Analog Code (C language pseudocode)
GPO 4 High Output:
unsigned char data;
data = inportb(0xC10); //First read corresponding IO Space register value
data |= 0x08;
Read GPI 9 Input Value:
unsigned char data;
data = inportb(0xC14); //first read corresponding IO Space register value
if (data & 0x01);
else
ITA-3650G_Series User Manual
0xC10:bit0~bit7 GPO(1~8)
0xC11:bit0~bit7 GPO(9~16)
0xC12:bit0~bit7 GPO(17~24)
0xC13:bit0~bit7 GPI(1~8)
0xC14:bit0~bit7 GPI(9~16)
0xC15:bit0~bit7 GPI(17~24)
//00001000B set bit 03 as'1', meaning output High
outportb(0xC10, data); //output value
//00000001B, judge value of bit 0
High // 1 = High
Low // 0 = Low
R/W
R
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