Receive Using Receive Fifo Buffers - Renesas RH850 Series Application Note

RH850 Series
3.

Receive Using Receive FIFO Buffers

There are 8 receive FIFO buffers shared by all channels. Messages can be stored in each receive FIFO buffer for the
number of buffers.
When a received message is stored in the receive FIFO buffer, the value of the corresponding message count display
counter (the RFMC [7: 0] bit of the RFSTSx register) is incremented.
Received messages can be read from the RFIDx register, RFPTRx register, RFFDSTSx register, and RFDFd_x
register (d = 0 to 15). The receive FIFO buffer can be read from the oldest message.
When the value of the message count display counter matches the buffer value of the FIFO buffer (the value set by
the RFCCx register RFDC [2: 0] bit), the receive FIFO buffer becomes full (the RFFLL flag in the RFSTSx register is
"1"). When all messages are read from the receive FIFO buffer, the receive FIFO buffer becomes empty (the RFEMP
flag in the RFSTSx register is "1").
Refer to the CAN Configuration Application Note for configuration settings to use the receive FIFO buffer.
Figure 3-1 shows the operation of the receive FIFO buffer.
Msg1 Msg2
：When the receive FIFO interrupt source reaches "the condition set in (the RFIGCV [2: 0] bit of the
RFCCx register) "
(When the RFIM bit of the RFCCx register is "0")
：Receive FIFO interrupt source is "every time one message is received"
(When the RFIM bit of the RFCCx register is "1")
R01AN6028EJ0100 Rev.1.0
May 10, 2017
CAN Bus
Msg3 Msg4
Figure 3-1 Receive FIFO Buffer Operation
CAN Receive Procedure (CAN FD Mode)
Receive FIFO
Buffer x
Msg4
Msg3
Msg2
Mag1
RFIDLm,Hx
RFTSmx
RFPTRx
RFDFx
Read with the
program
※ ： Number of receive FIFO
buffer stages: 4
An interrupt occurs when a
message is stored until 8/8
※
Receive
FIFO
interrupt
source
activated
Received data
Msg1
Msg2
Msg3
Msg4
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