Mux Diagram For Gpmc/Vin1/Vout3; Soc Pinmux For Gpmc/Emmc - Texas Instruments DRA72 Series User Manual

Signal Multiplex Logic
Mux B: Selects between NOR/NAND memories, FPD Linkl for video, and expansion, as shown in
Figure 10. The selection is made using the IO expander #2, and bits P7 and P0. The defaults are set to
enable GPMC to NOR/NAND memories, required for SYSBOOT mode latching.
SoC
4.3 GPMC and EMMC Selection (Mux C)
Figure 11 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): A[27:19], CS1
• EMMC Memory (MMC2): CLK, CMD, D[7:0]
26
DRA72x EVM CPU Board User's Guide
A1=B1 or A1=B2 or A1 = B3
CBT16214
A1
GPMC_A[12:0], _AD[15:0]
Mux
B3
Figure 10. Mux Diagram for GPMC/VIN1/VOUT3
Figure 11. SoC Pinmux for GPMC/EMMC
Copyright © 2016, Texas Instruments Incorporated
GPMC
GPMC_A[12:0], _AD[15:0]
B1
VOUT3
B
VOUT3_CLK, _VS, _HS, _DE,
_D[23:0]
B2
VIN1A
VIN1A_CLK, _VS, _HS, _DE, _D[23:0]
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DIP Switch
(SYSBOOT)
NOR Memory
NAND
Memory
FPD Link
Transmitter
Expansion
Connector
SPRUIB9 – December 2016
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