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User's Guide
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module
(EVM)
This technical user's guide describes the hardware architecture and configuration options of the J721E/DRA929/
TDA4VM EVM.
1
Introduction.............................................................................................................................................................................4
Features......................................................................................................................................................................4
1.2 Thermal Compliance..........................................................................................................................................................
Compliance...........................................................................................................................................................6
1.4 EMC, EMI, and ESD Compliance......................................................................................................................................
Overview..............................................................................................................................................................6
2.1 J721E EVM Board Identification........................................................................................................................................
2.2 J721E SOM Component Identification...............................................................................................................................
2.3 Jacinto7 Common Processor Components Identification................................................................................................
Setup/Configuration............................................................................................................................................12
Requirements........................................................................................................................................................12
3.2 Power ON Switch and Power LEDs.................................................................................................................................
3.3 EVM Reset/Interrupt Push Buttons..................................................................................................................................
3.4 EVM DIP Switches...........................................................................................................................................................
3.5 EVM UART/COM Port Mapping.......................................................................................................................................
3.6 JTAG Emulation...............................................................................................................................................................
4 J721E EVM Hardware Architecture.....................................................................................................................................
4.2 J721E EVM Interface Mapping........................................................................................................................................
Mapping.......................................................................................................................................................29
4.4 GPIO Mapping.................................................................................................................................................................
4.5 Power Supply...................................................................................................................................................................
4.6
Reset................................................................................................................................................................................38
4.7 Clock................................................................................................................................................................................
4.8 Memory Interfaces...........................................................................................................................................................
4.9 MCU Ethernet Interface...................................................................................................................................................
Interface.............................................................................................................................................50
Interface.................................................................................................................................................................52
Interface.................................................................................................................................................................58
Interface.................................................................................................................................................................61
4.14 FPD Interface (Audio Deserializer)................................................................................................................................
4.15 FPD Panel Interface (DSI Video Serializer)...................................................................................................................
4.17 Audio Interface...............................................................................................................................................................
Interface.....................................................................................................................................................68
Interface.................................................................................................................................................................68
Interface...................................................................................................................................................................70
Interface.................................................................................................................................................................70
4.22 RTC Interface.................................................................................................................................................................
4.23 Apple Authentication Header.........................................................................................................................................
4.24 EVM Expansion Connectors..........................................................................................................................................
4.25 ENET Expansion Connector..........................................................................................................................................
SPRUIS4D - MAY 2020 - REVISED MARCH 2022
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ABSTRACT
Table of Contents
Identification........................................................................................................................11
Diagram........................................................................................................................26
FPC.................................................................................................................................66
Copyright © 2022 Texas Instruments Incorporated
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
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Summary of Contents for Texas Instruments J721E
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Page 1: Table Of Contents
Table of Contents User’s Guide Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) ABSTRACT This technical user's guide describes the hardware architecture and configuration options of the J721E/DRA929/ TDA4VM EVM. Table of Contents Introduction.....................................4 1.1 Key Features..................................4 1.2 Thermal Compliance................................1.3 REACH Compliance................................6... - Page 2 Figure 1-1. Thermal Caution................................5 Figure 2-1. J721E EVM Board..............................6 Figure 2-2. System Architecture Interface........................... Figure 2-3. J721E EVM Board Identification (SOM, CPB, QP Ethernet)..................8 Figure 2-4. J721E SOM Component Identification........................Figure 2-5. Jacinto7 Common Processor Component Identification..................Figure 2-6. Quad Ethernet Component Identification.........................11...
- Page 3 Table 3-14. TI14 Pin Connector (J2-Refer PROC081E2 SCH) Pinout..................Table 4-1. J721E EVM Interface Mapping..........................Table 4-2. J721E EVM I2C Table...............................29 Table 4-3. J721E SoC - GPIO Mapping Table........................... Table 4-4. DDR I/O Voltage Selection............................34 Table 4-5. J721E SoC S2R Logic Flow............................35...
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Page 4: Introduction
It is a super-set processor/device and may be available is different configurations targeted for specific markets. This EVM will support development of the super-set device (J721E) as well as the market specific devices (DRA829/TDA4xM). Many features of the J721E system are available on the EVM, which gives developers the basic resources needed for most general-purpose type. -
Page 5: Thermal Compliance
Although the processor/heatsink is not a burn hazard, caution should be used when handling the EVM due to increased heat in the area of the heatsink. Figure 1-1. Thermal Caution SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 6: Reach Compliance
The product is used in the basic electromagnetic environment as in laboratory conditions, and the applied standard is as per EN IEC 61326-1:2021. 2 J721E EVM Overview Figure 2-1. J721E EVM Board Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright ©... -
Page 7: Figure 2-2. System Architecture Interface
Only one board can be connected to CSI2 Expansion connector at a time. Figure 2-2. System Architecture Interface The J721E EVM System on Module (SoM) board, a Jacinto7 Common Processor board, and Quad-Port Ethernet Board. Detailed descriptions of these cards are explained in the following sections. -
Page 8: J721E Evm Board Identification
J721E EVM Overview www.ti.com 2.1 J721E EVM Board Identification Figure 2-3. J721E EVM Board Identification (SOM, CPB, QP Ethernet) Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 9: J721E Som Component Identification
& Power OSPI J5 (DSI0, & DP0) Hyper Flash+ FLASH Hyper RAM Figure 2-4. J721E SOM Component Identification SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 10: Jacinto7 Common Processor Components Identification
Socket Battery Holder Test Automation RGMII DSI FPC Link Connector Serializer Figure 2-5. Jacinto7 Common Processor Component Identification Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 11: Quad Ethernet Components Identification
Because the Jacinto7 Common Processor board is used with different SOM boards featuring different Jacinto7 processors with different feature sets, some of the board’s peripherals/interfaces may not be supported. For the J721E SOM, the following interfaces are not supported: •... -
Page 12: Evm User Setup/Configuration
EVM’s 2.5 x 5.5-mm DC barrel jack connector (J7) supports 10-A current rating. Polarity outside barrel is Negative/GND, inside post is Positive/PWR. Figure 3-1. Connector Used for Power Input Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback... -
Page 13: Power On Switch And Power Leds
The power to the EVM is controlled by the power ON/OFF switch (SW2) on the CPB. To turn the board ON, slide the switch in the direction as shown in Figure 3-2. Figure 3-2. Power ON/OFF Switch SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 14: Figure 3-3. Power On/Fault Leds
Input voltage is >28 V or <6 V Input voltage is within the limit Figure 3-3. Power ON/Fault LEDs Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 15: Figure 3-4. Power Status Leds
Regulated Power On/Off VSYS_3V3 SoC Main Domain On/Off VSYS_IO_3V3 SoC MCU Domain On/Off VSYS_MCUIO_3V3 Figure 3-4. Power Status LEDs SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 16: Table 3-4. Power Test Points
VDD_SD_DV TP44 3.3V VSYS_MCUIO_3V3 TP113 3.3V VSYS_IO_3V3 TP131 3.3V VSYS_MCUIO_1V8 TP134 1.8V VSYS_IO_1V8 TP132 1.8V VDA_MCU_1V8 TP105 1.8V Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 17: Evm Reset/Interrupt Push Buttons
MCAN0_WAKE CAN Wakeup Input RESET PUSH BOTTOMS SW10 EXTINTn SW11 SYS_IRQz SW12 CAN_WK Figure 3-5. EVM Push Buttons SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 18: Evm Dip Switches
EVM User Setup/Configuration www.ti.com 3.4 EVM DIP Switches J721E EVM supports User DIP Switches for EVM Configuration and SoC Boot mode set function. 3.4.1 EVM Configuration DIP Switch Figure 3-6 shows that the common processor board has a dedicated EVM configuration switch (SW3) to set the various functions of EVM peripherals. -
Page 19: Table 3-6. Evm Configuration Switch Function
USER_INPUT1 User Define, maps to I/O Expander Input ‘0’ (OFF) = User Defined ‘1’ (ON) = User Defined SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 20: Table 3-7. Evm Configuration Switch Function
EVM User Setup/Configuration www.ti.com 3.4.2 SOM Configuration DIP Switch Table 3-7 shows the J721E SOM configuration switches (SW1-SW3) to set the various functions SOM. Table 3-7. EVM Configuration Switch Function Switch Default Name Condition Signal Operation SW1.1 LPDDR4_IO_SEL Selects the I/O voltage level for LPDDR4: ‘0’... -
Page 21: Figure 3-7. Boot Switches Provided On The Processor Card
(SW8.6) (SW8.7) (SW9.8) Primary Boot Backup Boot Mode Primary Boot Mode Config Backup Boot Mode B Mode Config SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 22: Evm Uart/Com Port Mapping
The ID and VBUS supply pin of USB connectors is connected to the DIP switch SW1 to configure the operational modes. As previously mentioned, the USB2 port, USB3.0 microAB interface is not supported with the J721E SoM. 3.5 EVM UART/COM Port Mapping Four main domain UART ports of the SoC are interfaced with FT4232H for UART-to-USB functionality and terminated on a micro B connector (J44) provided on the CPB. -
Page 23: Jtag Emulation
Function XDS110 Powered via USB HIGH A<->B2 port [On Board EMU] External Emulator attached A<->B1 port [EXTERNAL EMU] SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 24: Table 3-12. Ti 60 Pin Connector (J16) Pinout
DGND TRC_CTL TRC_DATA14 TRC_DATA19 TRC_DATA0 TRC_DATA15 TRC_DATA20 TRC_DATA1 TRC_DATA16 TRC_DATA21 TRC_DATA2 TRC_DATA17 TRC_DATA3 TRC_DATA18 TRC_DATA4 DGND JTAG_MUX_SEL TRC_DATA5 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 25: Table 3-13. Cti20 Pin Connector (J1-Refer Proc081E2 Sch) Pinout
Pin No. Signal MIPI_14_TMS 14PJTAG_DET MIPI_14_TRST MIPI_14_RTCK MIPI_14_TDI DGND MIPI_14_TDIS MIPI_14_TCK MIPI_14_VTREF DGND NC (key) MIPI_14_EMU0 MIPI_14_TDO MIPI_14_EMU1 SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 26: J721E Evm Hardware Architecture
J721E EVM Hardware Architecture www.ti.com 4 J721E EVM Hardware Architecture This section explains the Hardware Architecture of J721E EVM in detail. 4.1 J721E EVM Hardware Top level Diagram Figure 4-1 shows the functional block diagram of the J721E EVM. Figure 4-1. J721E EVM Functional Block Diagram Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D –... -
Page 27: Figure 4-2. Quad Port Ethernet Expansion Functional Block Diagram
3.3 V REGULATOR TPS74801 (x2) POWER(12 V, 5 V, 3V3) Figure 4-2. Quad Port Ethernet Expansion Functional Block diagram SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 28: J721E Evm Interface Mapping
J721E EVM Hardware Architecture www.ti.com 4.2 J721E EVM Interface Mapping Table 4-1 shows the J721E EVM Interface Mapping table. Table 4-1. J721E EVM Interface Mapping Interface Name Port on SoC Device Part Number Memory – LPDDR4 DDR0 MT53D1024M32D4DT Memory – OSPI... -
Page 29: I2C Address Mapping
J721E EVM Hardware Architecture 4.3 I2C Address Mapping Table 4-2 shows the complete I2C address mapping details on the EVM. Table 4-2. J721E EVM I2C Table J721E EVM I2C Table Board I2C Port Device/Function Part# I2C Address EVM/SoM WKUP_I2C0... -
Page 30: Gpio Mapping
The general purpose I/Os (GPIOs) of the SoC have two major groups: WKUP/MCU and MAIN. Table 4-3 describes the detailed GPIO mapping of SoC with EVM peripherals. Table 4-3. J721E SoC - GPIO Mapping Table J721E SoC - GPIO Mapping Table Package Signal... -
Page 31: Power Supply
SoM’s power distribution system. The Power to the SoM is derived from the Dual Buck converter 12 V to 5.0 V / 3.3 V on the Common Processor Board. The J721E processor is powered from a dual TPS6594x PMIC solution, which is optimized for the J721E to support a wide variety of use cases. -
Page 32: Figure 4-4. Power On Sequencing
UB926_PWR_SW_CNTRL* LM5141_PG LM5140_PG2 PORz PMIC_PORz LOAD SW PCIe0_PORz VCC_12V_DSI0 TPS1H100A PWR_SW_CNTL_DSI0* PCIe1_PORz TA_PORZ# Figure 4-4. Power ON Sequencing Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 33: Figure 4-5. Voltage Supervisor Circuit
The power rails are monitored to control the Power ON Reset (MCU_PORz) for SoC. Two supervisor devices are provided to monitor Main power input and VSYS_3V3. Figure 4-5. Voltage Supervisor Circuit SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 34: Figure 4-6. Lpddr4 Io Voltage Selection Circuit
4.5.3 DDR I/O Voltage Selection There is a DIP switch provided on the J721E SoM to select the SoC’s DDR and LPDDR4 memory I/O supply for the LPDDR4/LPDDR4x. Currently, the J721E device does not support LPDDR4x. This support may be added at a later date. The EVM does support this feature if/when support is added to the silicon. -
Page 35: Table 4-5. J721E Soc S2R Logic Flow
J721E EVM Hardware Architecture 4.5.3.1 J721E SoC S2R Logic Flow Diagram The EVM supports a low power state referred to as Suspend-to-RAM (or S2R). This state allows the processor (or optionally the entire system) to be powered off while the LPDDR4 memory is maintained in self refresh mode. -
Page 36: Table 4-7. Ina Devices I2C Slave Address
4.5.3.3 Power Monitoring INA226 power monitor devices are used to monitor current and voltage of various power rails of J721E processor. The device reports current, voltage and power to J721E processor through I2C interface. Four Terminal High Precision shunt resistors are provided, and the values are calculated based on load current. -
Page 37: Table 4-8. External Power Monitor Header Pinouts
DGND CON_PM2_SDA CON_PM2_SCL Test automation header on the Common processor board also can access these INA devices externally. SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 38: Reset
J721E EVM Hardware Architecture www.ti.com 4.6 Reset Figure 4-7 shows the J721E EVM reset architecture. Figure 4-7. EVM Reset Architecture Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 39: Clock
J721E EVM Hardware Architecture 4.7 Clock Figure 4-8 shows the J721E EVM clock architecture. CP Board PCIe Slot 100MHz P/N 100MHz P/N SERDES0 (x1L) 100MHz P/N PCIe Slot 100MHz P/N SERDES1 (x2L) Clock 25MHz Generator CDCI6214 XTAL PCIe Slot... -
Page 40: Figure 4-9. J721E Soc Primary Clock
The WKUP_OSC0 is required by the processor. Both WKUP_LFOSC and OSC1 are optional clocks (not required for J721E processing). The WKUP_LFOSC can be sourced either on the on-board crystal or from the PMIC. The OSC1 can be sourced from either the on-board crystal or from clock generator (CDCEL937) on the Common Processor board. -
Page 41: Table 4-9. Processor's Secondary/Serdes Ref Clock
(CDCI6214) on the Common processor board. All these clocks are 100 MHz with HCSL level for the SoC’s SERDES reference clock input. The programming of CDCI6214 chip is done through J721E SoC’s I2C0 port. There are two CDCI6214 clock generators available to source the SERDES reference clocks to SoC. The CDCI1 (U22) is not connected to I2C0 port by default. -
Page 42: Memory Interfaces
4.8.1 LPDDR4 Interface The J721E SOM has 4GB of LPDDR4 using single 32Gb x 8-bit wide memory devices arranged in an 32-bit wide bus. The LPDDR4 interface can operate up to 3733 Mb/s speed. The LPDDR4 device is connected using T-branched routing for the clock and address/command lines and point-to-point connection for the data bus. -
Page 43: Figure 4-11. J721E Som Ospi And Hyper Flash
The J721E SOM has 512 Mbit OSPI memory device of part number MT35XU512ABA1G12-0SIT connected to OSPI0 interface of J721E processor. The OSPI interface supports single and double data rates with memory speed up to 166 MHz SDR and 200 MHz DDR. -
Page 44: Figure 4-12. Ufs Memory Block Diagram
The Common Processor board has 32GB UFS memory device Mfr. Part# THGAF8G8T23BAIL connected to UFS0 port of SoC. The UFS memory is Gear3/2Lane capable and supports UFS Version 2.1. Figure 4-12. UFS Memory Block Diagram Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback... -
Page 45: Figure 4-13. Emmc Memory Block Diagram
A 16GB, V5.1 compliant eMMC flash memory Mfr. Part# MTFC16GAPALBH-AAT ES is interfaced to MMC0 port of the J721E SoC. The flash is connected to 8 bits of the MMC0 interface supporting HS400 double data rates up to 200 MHz. External pull up resistors 49.9K are provided on DATA [7:0], CMD and Reset signals, pull down resistor is provided on the data strobe signal to prevent bus floating. -
Page 46: Figure 4-14. Micro-Sd Card Block Diagram
The CD (card detect) pin of Micro SD card socket is pulled high and connected to CD pin of SoC. An external pull up resistor (47K) is provided on data [3:0] and CMD signals to avoid floating. Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright ©... -
Page 47: Table 4-11. Board Id Memory Header Information
J721E EVM Hardware Architecture 4.8.5 Board ID EEPROM Interface The J721E EVM boards are identified by its version and serial number, which are stored in the onboard EEPROM. The EEPROM is accessible from WKUP I2C0 port of J721E processor. The board ID EEPROM I2C slave address of various boards are listed in the I2C mapping table. -
Page 48: Mcu Ethernet Interface
The I/O supply to the Ethernet PHY is set through selection Resistors R445 and R446 to support both 1.8 V and 3.3 V I/O level. The EVM is configured to 3.3 V I/O supply for MCU RGMII PHY I/O signals by default. Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright ©... -
Page 49: Figure 4-16. Mcu Ethernet Phy Settings
RMGII Clock Skew TX = 0ns RMGII Clock Skew TX = 2ns Figure 4-16. MCU Ethernet PHY Settings SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 50: Qsgmii Ethernet Interface
4.10 QSGMII Ethernet Interface The SERDES0 SGMII2 signals of J721E SoC is interfaced to Quad SGMII PHY VSC8514XMK-11 on the Quad Port Ethernet board through CP board, two stacked RJ45 connectors with integrated magnetics PN# LPJG17512AONL used for external communication. -
Page 51: Figure 4-17. Quad-Sgmii Board I2C
The address and clock configurations are shown below: • PHY0: 10000 0X10 • PHY1: 10001 0X11 • PHY2: 10010 0X12 • PHY3: 10011 0X13 SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 52: Pcie Interface
I2C0 from SoC is used for control purpose and is connected to SMBUS on the connector. I2C0 port is connected to both x1 lane and x2 lane PCIe connectors using a Mux TCA9543APWR. Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright ©... -
Page 53: Figure 4-19. Pcie Interface For Serdes0
I2C MUX TCA9543A SOC_I2C0_SCL 3.3 V I2CADD: 0x70 PCIe x2 Lane Socket Figure 4-20. PCIe SMBUS Block Diagram SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 54: Figure 4-21. 1L-Pcie Root Complex/Endpoint Selection Circuit
R198 R199, C93 Reference clock for SOC from PCIe R195, C92 R194, R109 connector R199, C93 R198, R110 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 55: Figure 4-22. Usb2.0 Header Connection
Also, USB2.0 data signals from USB HUB downstream port is interfaced to 4 pin header (J2) and the 5 V supply is provided through the load switch. Figure 4-22. USB2.0 Header Connection SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 56: Figure 4-23. Pcie Interface For Serdes1
Whereas, in case of PCIe end point operation, the CP board receives reset signal from the PCIe card. Figure 4-24. 2L-PCIe Root Complex/Endpoint Selection Circuit Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback... -
Page 57: Table 4-16. Reference Clock Selection For Pcie Host Operation
J721E EVM Hardware Architecture Clock: A clock generator (CDCI #1) is provided to drive 100 MHz HCSL clock for PCIe add on cards and J721e SoC. Resistor options are provided to select the clock source for host and end point operation. -
Page 58: Usb Interface
10K by default to ensure PCIe Reset (#PERST) remains asserted until SoC releases reset. Clock: A clock generator (CDCI #2) is provided to drive 100MHz HCSL clock for PCIe add on cards and J721E SoC. Resistor options are provided to select the clock source either from SoC or clock generator. -
Page 59: Figure 4-26. Usb3.1 Type C Interface
The control signals for Powerdown and VBUS enable are given from I2C GPIO Expander2 (I2C add: 0x22 - P03) and the SoC DRVVBUS, respectively. SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 60: Figure 4-28. Usb Hub Reference Clock Circuit
4.12.2 USB 2.0 Interface The USB1 port of J721E SoC is used for USB 2.0 interface in J721E EVM. The USB1 signals are connected to upstream port of USB 2.0 Hub (TUSB4041IPAPR). The four downstream ports from USB Hub are connected are shown below: •... -
Page 61: Can Interface
It is reserved for future development. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port) This is an optional interface provided for a future version of the J7 SoC only; it is not supported in the J721E EVM. -
Page 62: Figure 4-32. Can Wake Push Button
MCU CAN1 The MCU CAN1 port of J721E SoC is connected to the CAN transceiver Mfr. Part# TCAN1042HGVD. A 2-pin header J34 (68002-202HLF) is provided inline for user probe option. This port does not support WAKE function. The signals MCU_MCAN1_H and MCU_MCAN1_L are terminated to a 3-pin header J31 (FCI: 68001-403HLF) with 120E split termination. -
Page 63: Figure 4-33. Can Header Connections To Db9/Test Instrument
1.8V using a Zener diode and terminated to SOM -CP B2B connector. MAIN CAN2 The MAIN CAN2 port of J721E SoC is connected to the CAN transceiver Mfr. Part# TCAN1042HGVD. A 2-pin header J25 (68002-202HLF) is provided inline for user probe option. This port does not support WAKE function. -
Page 64: Fpd Interface (Audio Deserializer)
(SN74CBT16214CDGGR). The channel selection is supported by both GPIO expander and EVM configuration DIP switch (SW3). The I2C3 signals of J721E being used for controlling of the De-serializer. A 40.2KΩ pull down is provided on ID[X] pin to set the 7‘b I2C address to 0x2C. -
Page 65: Fpd Panel Interface (Dsi Video Serializer)
ASDMB-25.000MHZ-XY-T with the resistor option. The default clock source is selected to onboard clock oscillator. The I2C1 signals of J721E being used for controlling of the FPD bridge. A 30.1KΩ pull up and 61.9KΩ pull down is provided on ID[X] pin to set the 7‘b I2C address to 0x16. -
Page 66: Display Serial Interface (Dsi) Fpc
4.16 Display Serial Interface (DSI) FPC The J721E EVM supports DSI interface over FPC connector 52559-3652 by using the resistor mux on the J721E DSI0 port. By default, the resistor mux is set to route the DSI0 signals to FPD Serializer. The power (12 V and 3.3 V), I2C1 interface and GPIO controls (RESET and INTn) are supported in the DSI FPC connector to... -
Page 67: Figure 4-37. Audio Port Interface Assignment
Line-IN R VIN6 MIC R VIN4 Line-OUT R VOUT8 HPOUT R VOUT4 Figure 4-37. Audio Port Interface Assignment SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 68: Display Port Interface
P signals respectively. The reset signal that comes from the expander (I2C ADD# 0x22, I2C0) is availed with a pull down to avoid floating, and the interrupt signal is equipped with a pull up and routed to J721E SoM. -
Page 69: Figure 4-39. Mlb Interface Connector
H_MLB0_MLBSIG MLB0_MLBDAT_N H_MLB0_MLBDAT MLB0_MLBDAT_P H_MLB0_REFCLK MLB0_MLBCLK_N MLB0_MLBCLK_P DGND DGND MLB0_GPIO0 MLB_RSTz I2C0_SCL MLB_INT# I2C0_SDA VSYS_IO_3V3 VSYS_IO_3V3 VSYS_IO_3V3 VCC_12V0 SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 70: I3C Interface
Common Processor board supports two I3C headers to validate the J721E SoC’s MCU and MAIN domain I3C interfaces. Out of Two I3C headers, only the MCU I3C header J33 is populated on J721E EVM and the MAIN I3C header J32 is not populated by default. MCU_I3C0_SDA is pulled through 1K Resistor by signal MCU_I3C0_SDAPULLEN from SoC. -
Page 71: Rtc Interface
DGND 4.22 RTC Interface A real-time clock module Mfr. Part# MCP79410-I/SN is connected I2C0 interface of J721E SoC. RTC device is being powered by 3.3 V and a battery holder BC501SM is connected to VBAT pin for external battery power option (battery not provided). A 32.768 kHz quartz crystal is used to provide clock for the device. -
Page 72: Apple Authentication Header
Module Interface: Common Processor board have a 2.54 mm Dual row 10 Pin Receptacle Mfr. Part# 2214BR‐10G. I2C0 Port of J721E SoC and Reset from GPIO Expander is terminated to this connector. 3.3 V supply is provided to the connector J9. -
Page 73: Evm Expansion Connectors
In this approach Common Processor PCB have a footprint PG‐USON‐8‐1. Apple authentication device will not be assembled to this footprint by default. Required I2C0, Power, Reset and Ground signals from J721E SoC is routed to this footprint, as shown in Table 4-28. -
Page 74: Table 4-29. Evm Expansion Connector J46
MCASP0_AXR2/PRG0_RGMII1_RX_CTL MCASP0_AXR7/PRG0_RGMII1_TD0 MCASP0_AXR4/PRG0_RGMII1_RXC MCASP0_AXR11/PRG0_RGMII1_TX_CTL PRG0_RGMII1_RD2 MCASP0_AXR10/PRG0_RGMII1_TD3 MCASP0_AXR1/PRG0_RGMII1_RD1 MCASP0_AXR9/PRG0_RGMII1_TD2 PRG0_RGMII1_RD3 MCASP0_AXR12/PRG0_RGMII1_TXC DGND DGND MCASP1_AXR8/PRG0_RGMII2_TD1 MCASP6_ACLKX/PRG1_RGMII1_RD0 MCASP1_AXR7/PRG0_RGMII2_TD0 MCASP6_AFSR/PRG1_RGMII1_RXC GPIO0_79/PRG0_RGMII2_TXC MCASP6_AFSX/PRG1_RGMII1_RD1 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 75 PRG0_MDIO0_MDIO/I2C5_SCL SPI3_D0 MCASP0_AXR13/PRG0_PWM0_B2 SPI3_D1 SPI3_CLK RGMII_REFCLK DGND DGND I2C0_SCL MCASP1_ACLKX I2C0_SDA SOC_I2C2_SCL I2C1_SCL SOC_I2C2_SDA I2C1_SDA EXP_RSTz DGND DGND SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 76: Table 4-30. Evm Expansion Connector J51
GPMC0_A18 GPMC0_A10 GPMC0_A19 GPMC0_A12 GPMC0_A13 DGND DGND DGND VSYS_5V0 DGND VSYS_5V0 DGND VSYS_5V0 MCU_ADC1_AIN0 MCU_ADC1_AIN1 MCU_ADC1_AIN2 MCU_ADC1_AIN3 MCU_ADC1_AIN4 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 77: Enet Expansion Connector
The Reference clock to the PHY is generated from TI’s Clock Generator Mfr. Part Number# CDCI6214RGET that is placed on the Common Processor (CPU) Board. Clock inputs shall be AC coupled and LVDS compliant. The clock generator can be configured by I2C0 of the J721E SoC. The I2C address of this clock generator is 0x77. -
Page 78: Figure 4-44. Cdci I2C Isolation Circuit
CDCI6214RGET, located on Quad port Ethernet Expansion Board, which can be configured by I2C0 of the J721E SOC. The I2C address of this clock generator is 0x77 and this address conflicts with CDCI Chip on Common processor Board. An I2C switch on Quad port Ethernet Expansion Board is used to remove the address conflict by either connecting any one of the clock generators. -
Page 79: Table 4-32. Enet Expansion Connector J10 Pinout
WKUP_I2C0_SDA DGND I2C0_SCL I2C0_SDA DGND VCC_12V0 VCC_12V0 DGND ENET_EXP_PWRDN QSGMII_INTN DGND QSGMII4_TX_P QSGMII4_TX_N DGND QSGMII4_RX_P QSGMII4_RX_N DGND QSGMII_PHY_REFCLK_N SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 80 J1B, J2A and J2B) from the SERDES domain of J721E processor are used. 4.25.4.1 Quad Port SGMII PHY Default Configuration The J721E EVM uses the 138-pin QFN package, designated with the XMK suffix that supports only the SGMII interface.
- Page 81 QSH-020-01-L-D-DP-A-K with 5 mm mating height allowing CSI Expansion to be stacked on bottom side of the processor board. Camera Serial Interface CSI0 and CSI1 of J721E SoC is interfaced to this CSI expansion connector J52 on the CP board. The Common Processor board supports the Auxiliary CSI expansion connector that is reserved for CSI2 port of future J7 SoC.
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Page 82: Table 4-33. Csi Expansion Connector J52 Pinout
CSI2_RX0_P CSI2_B_REFCLK_DV EXP_3V3 CSI2_RX0_N DGND EXP_3V3 CSI2_RX1_P CSI2_RSTZ_DV EXP_3V3 CSI2_RX1_N DGND EXP_3V3 CSI2_RX2_P CSI2_B_GPIO2_DV VCC_CSI_IO CSI2_RX2_N CSI2_B_GPIO3_DV VCC_CSI_IO Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 83 Changes from Revision C (February 2022) to Revision D (March 2022) Page • Updated EMC, EMI, and ESD Compliance section.................... SPRUIS4D – MAY 2020 – REVISED MARCH 2022 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 84 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...
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