Reset Signals Structure - Texas Instruments DRA72 Series User Manual

Hardware
Table 9 summarizes the reset signals.
Reset Type
Power-on reset (as whole system reset)
Warm reset
PMIC power-on reset
Processor reset out
3.4 Clocks
The SoC supports three primary clock inputs. The device clock (OSC0) is provided by a 20-MHz crystal,
and the auxiliary clock (OSC1) is provided by a 22.5792-MHz crystal. The RTC clock input is provided by
a 32.768-KHz crystal.
In addition to the SoC clock inputs, the EVM includes other clock sources. A 25-MHz oscillator is provided
to a CDCM9102 clock driver for sourcing the PCI 100-MHz reference clock. Each Ethernet PHY also
includes a local 25-Mhz crystal to provide its network reference clock.
3.5 Memory
3.5.1 SDRAM Memory
The EVM includes 2 GBytes of DDR3L memory, and can operate at clock speeds up to 667 MHz (DDR3-
1333). The memory is configured with four devices of 4 Gbit each (x8b devices). ECC is also supported.
DDR3L device used: Micron MT41K512M8RH-125-AA:E (4 × 8bit at 4 Gbit/ea) (or equivalent).
EEC device used: Micron MT41K512M8RH-125-AA:E (1 × 8bit at 4 Gbit) (or equivalent).
The DDR3L power is generated from the PMIC (TPS65917-Q1) and set to 1.35 V. It uses fly-by topology
with VTT termination. VTT supply is generated using a sink and source termination regulator (TPS51200).
3.5.2 QSPI Flash Memory
As a primary non-volatile boot device, the EVM includes 256 Mbit of Quad-SPI flash memory. The device
is supported on chip select zero of the QSPI interface. The interface can be configured to support either
serial mode (1x) or quad mode (4x).
QSPI device used: Spansion S25FL256S
Booting from the QSPI flash memory is supported on the EVM. No EVM configuration is required, as the
QSPI flash is connected by default. Ensure the correct SoC boot mode using the SYS_BOOT switches
(SW2, SW3).
3.5.3 EMMC Flash Memory
As a primary non-volatile storage device, the EVM includes 8 GBytes of eMMC flash memory. The
memory device is EMMC v4.51-compliant, and connects to MMC2 port of the SoC. The design can
supports rates up to HS-200.
EMMC device used: Micron MTFC8GLWDM-3M AIT Z
Booting from the EMMC flash memory is supported on the EVM. The on-board mux must be set to enable
EMMC by setting the SW5.p3 to ON. Ensure the correct SoC boot mode is set using the SYS_BOOT
switches (SW2, SW3).
12
DRA72x EVM CPU Board User's Guide
Table 9. Reset Signals Structure
Reset Signal Sources
CPU_POR_RESETn
PCI_PORz
PMIC_RESET_OUT
CPU_RESETn
EMU_RSTn
PMIC_RESET_IN
RSTOUTn
Copyright © 2016, Texas Instruments Incorporated
Comments
PORn push button reset
PCIe inbound reset
Power on reset from PMIC
Warm push button reset
Reset from emulator
PMIC reset input
Reset output from processor to system,
PMIC (warm reset input)
SPRUIB9 – December 2016
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