Table 35: Control Byte C1, Version 750-637/000-004 - WAGO 750-637 Series Manual

WAGO I/O System 750
750-637 Incremental Encoder Interfaces

Table 35: Control byte C1, Version 750-637/000-004

Bit 7
0
MapPZD
INV_GATE
SetNocke1_F2
SetNocke2_F2
SetCam1_F1
SetCam2_F1
Enable_Cams
0
Control Byte C1
Bit 6 Bit 5
Enable_ Set
Cam Cam2_ Cam1_
F1
Coding of Process Data
0: Counter value
1: Latch value
Coding of Process Data
The counting process is disabled when 24 V is applied to
0:
the GATE input.
The counting process is disabled when 0 V is applied to
1:
the GATE input or when the input is open.
NOTICE:
The request is not acknowledged in the status byte!
Apply Cam Output 1, Window 2
Set value applied as lower comparison value N1F2_LO
Positive edge:
for cam output 1 (N1) window F2
Set value applied as the upper comparison value
Negative edge:
N1F2_HI for cam output 1 (N1) window F2
Apply Cam Output 2, Window 2
Set value applied as lower comparison value N2F2_LO
Positive edge:
for cam output 2 (N2) window F2
Set value applied as the upper comparison value
Negative edge:
N2F2_HI for cam output 2 (N2) window F2
Apply Cam Output 1, Window 1
Set value applied as lower comparison value N1F1_LO
Positive edge:
for cam output 1 (N1) window F1
Set value applied as the upper comparison value
Negative edge
N1F1_HI for cam output 1 (N1) window F1
Apply Cam Output 2, Window 1
Set value applied as lower comparison value N2F1_LO
Positive edge:
for cam output 2 (N2) window F1
Set value applied as the upper comparison value
Negative edge
N2F1_HI for cam output 2 (N2) window F1
Output Voltage
All cam outputs are inhibited, i.e., the output voltage is
0:
0 V
Alle cam outputs are enabled, i.e., the output voltage is
1:
24 V
The request is acknowledged in the status bit Enable_Cams (S0.3).
Reserved
Public
Bit 4 Bit 3 Bit 2
Set Set Set
Cam2_ Cam1_
F1 F2 F2
Process Image 43
Bit 1 Bit 0
INV_ MapPZD
GATE
Manual
Version 1.6.1