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Two operands
D
Be subtracted data and result address
S1
Subtract data address
Suitable soft component
Operand
Word
Three operands
S1
S2
D
Two operands
D
S1
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
Description
<Three operands>
appoint the soft unit's content, subtract the soft unit's content appointed by
format of algebra. The result will be stored in the soft unit appointed by
The action of each flag, the setting method of 32 bits operation's soft units are both the same
with the preceding ADD instruction.
The importance is: in the preceding program, if X0 is ON, SUB operation will be executed
every scan cycle.
Refer to chapter 4-6-1 for flag action and functions.
<Two operands>
appoint the soft unit's content, subtract the soft unit's content appointed by
S1·
format of algebra. The result will be stored in the soft unit appointed by
The action of each flag, the setting method of 32 bits operation's soft units are both the same
with the preceding ADD instruction.
The importance is: in the preceding program, if X0 is ON, SUB operation will be executed
every scan cycle. Rising or falling pulse edge is recommended to activate the instruction.
Refer to chapter 4-6-1 for flag action and functions.
System
D *
FD
TD *
CD *
DX
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X0
SUB
(D10) — (D12) → (D10)
16 bits /32 bits,BIN
16 bits /32 bits,BIN
Constant
DY
DM *
DS *
K /H
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(D10) — (D12) → (D14)
D·
S1·
D10
D12
119
Module
ID
QD
in the
(5-(-8)=13).
in the
S2·
(5-(-8)=13)
D·
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