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3. Suitable soft components
Operand
Word
Three operands
S1
S2
D
Two operands
D
S1
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
Description
< Three operands>
Two source data do binary addition and send the result to target address. Each data's highest
bit is the sign bit, 0 stands for positive, 1 stands for negative. All calculations are algebraic
processed. (5+ (-8) =-3)
If the result of a calculation is "0", the "0" flag acts. If the result exceeds 323767 (16 bits
limit) or 2147483647 (32 bits limit), the carry flag acts. (refer to the next page). If the result
exceeds –323768（16 bits limit）or –2147483648 (32 bits limit), the borrow flag acts (refer
to the next page).
When doing 32 bits operation, word device's low 16 bits are assigned; the device close to the
preceding device's is the high bits. To avoid ID repetition, we recommend you assign
device's ID to be even number.
The source and target address can be the same. In the above example, when X0 is ON, the
instruction will be executed in every scanning period.
<Two operands>
X0
Two source data do binary addition and send the result to addend data address. Each data's
highest bit is the sign bit, 0 stands for positive, 1 stands for negative. All calculations are
algebraic processed. (5+ (-8) =-3)
If the result of a calculation is "0", the "0" flag acts. If the result exceeds 323767 (16 bits
limit) or 2147483647 (32 bits limit), the carry flag acts. (refer to the next page). If the result
System
*
*
*
D
FD
TD
CD
●
●
●
●
●
●
●
●
●
●
●
●
●
●
D·
S1·
ADD
D10
D12
(D10)＋ (D12) → (D10)
117
constant
*
*
DX
DY
DM
DS
K /H
●
●
●
●
●
●
●
●
●
●
●
●
●
●
(D10) ＋ (D12) → (D14)
Module
ID
QD
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