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D7
SRDYCTL: #SRDY Control Bit
Selects a control method for the #SRDYx signal.
1 (R/W): High mask mode
0 (R/W): Normal output (default)
When SRDYCTL is set to 0, the #SRDYx signal is controlled normally and indicates ready to receive
even if the receive data buffer is full. When SRDYCTL is set to 1, high-mask mode is selected. The fol-
lowing shows the #SRDYx controls in clock-synchronized slave mode and master mode:
Clock-synchronizes slave mode
When the receive data buffer is full, the #SRDYx signal is forcibly fixed at high in order to suspend
data transfer from the master device until the data in the buffer is read.
Clock-synchronized master mode
When the receive data buffer is full, the #SRDYx signal (low) from the slave device is ignored and
the serial interface stops outputting the SCLKx signal until the buffer data is read.
The high mask mode can avoid overrun errors.
When the receive data buffer is not full, normal receive operations are performed even if this function is
enabled.
In asynchronous mode, this bit is ignored as it does not use the #SRDYx signal.
Note: This bit can be rewritten only when SIOADV/FSIO_ADVx register is set to 1 (advanced mode).
D[6:5]
FIFOINT[1:0]: Receive Buffer Full Interrupt Timing Bits
Sets the number of data in the receive data buffer to generate a receive-buffer full interrupt.
Writing 0–3 to FIFOINT[1:0] sets the number of data to 1–4. When the number of data in the receive
data buffer reaches the number specified here, the receive-buffer full interrupt flag RDBF_IF/FSIO_
INTFx register is set to 1.
Note: This bit can be rewritten only when SIOADV is set to 1 (advanced mode).
D4
DIVMD: Async Clock Division Ratio Bit
Selects the division ratio for the sampling clock.
1 (R/W): 1/8
0 (R/W): 1/16 (default)
Select the division ratio to generate the sampling clock for asynchronous transfers. When DIVMD is
set to 1, the sampling clock is generated from the input clock of the serial interface (output from the
baud-rate timer or input from SCLKx) by dividing it by 8. When DIVMD is set to 0, the input clock is
divided by 16.
D3
IRTL: IrDA I/F Output Logic Inversion Bit
Inverts the logic of the IrDA output signal.
1 (R/W): Inverted
0 (R/W): Not inverted (default)
When using the IrDA interface, set the logic of the SOUTx output signal to suit the infrared-ray com-
munication circuit that is connected external to the chip. If IRTL is set to 1, a high pulse is output when
the output data = 0 (held low-level when the output data = 1). If IRTL is set to 0, a low pulse is output
when the output data = 0 (held high-level when the output data = 1).
S1C33L26 TECHNICAL MANUAL
Table 20.
10.4 Number of Receive Data Buffer
FIFOINT[1:0]
0x3
0x2
0x1
0x0
Seiko Epson Corporation
20 GENERAL-PURPOSE SERIAL INTERFACE (FSIO)
Receive level
4
3
2
1
(Default: 0x0)
20-27
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