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Transfer mode
8-bit asynchronous mode
7-bit asynchronous mode
Clock-synchronized slave mode
Clock-synchronized master mode
All four pins are used in the clock-synchronized mode.
In the asynchronous mode, since no ready signal is used, the #SRDYx pin can be used as an I/O (P) port. In addi-
tion, when an external clock is not used, the SCLKx pin can also be used as an I/O port.
The I/O control and data registers for the I/O ports used in the serial interface can be used as general-purpose read/
write registers.
20.4.2
Standard Mode and Advanced Mode
The serial interface in the S1C33L26 is extended from that of the C33 STD models. This serial interface has two
operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and
an advanced (ADV) mode allowing use of the extended functions. Table 20.4.2.1 shows differences between stan-
dard mode and advanced mode.
Table 20.
Function
#SRDY mask control
Number of received data in the buffer to
generate a receive-buffer full interrupt
To configure the serial interface in advanced mode, set SIOADV/FSIO_ADVx register to 1. The control bits for the
extended functions are enabled to write after this setting. At initial reset, SIOADV is set to 0 and the serial interface
enters standard mode.
The following descriptions unless otherwise specified are common contents for both modes. The extended func-
tions in advanced mode are explained assuming that SIOADV has been set to 1.
20.5
Baud-Rate Timer (Baud Rate Setting)
The clock-synchronized master mode uses an internal clock for data transfer. Also in the asynchronous mode, the
internal clock can be selected as the operating clock. Each channel has an embedded baud-rate timer (12-bit pro-
grammable timer) to generate this clock. The counter initial value can be set via software, this makes it possible to
program a flexible transfer rate/sampling frequency.
It is not necessary to configure and run the baud-rate timer, when this serial interface is used in the clock-synchro-
nized slave mode or in the asynchronous mode using an external clock.
PCLK1/PCLK2
Clock output
SIO_CLK
S1C33L26 TECHNICAL MANUAL
Table 20.
4.1.2 Pin Configuration by Transfer Mode
SINx
Data input
Data input
Data input
Data input
4.2.1 Differences between Standard Mode and Advanced Mode
Figure 20.
5.1 Transfer Clock Generation by the Baud-Rate Timer
Seiko Epson Corporation
20 GENERAL-PURPOSE SERIAL INTERFACE (FSIO)
SOUTx
Data output
Clock input/P port
Data output
Clock input/P port
Data output
Data output
Standard mode
Disabled
One
BRTRUN
12-bit reload data register
(BRTRD)
12-bit down counter
(BRTCD)
Buffer
Clock generator
SCLKx
#SRDYx
P port
P port
Clock input
Ready output
Clock output
Ready input
Advanced mode
Enabled
One to four can be specified.
Underflow
signal
20-3
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