Epson S1C33L26 Technical Manual page 690

Register name Address Bit
REMC Carrier 0x301502 D15–14 –
Length Setup
(16 bits) D13–8 REMCL[5:0] Carrier L length setup
Register
D7–6 –
(REMC_CAR)
D5–0 REMCH[5:0] Carrier H length setup
REMC Length 0x301504 D15–8 REMLEN[7:0] Transmit/receive data length count
Counter Register
(16 bits)
(REMC_LCNT) D7–1 –
D0
REMC Interrupt 0x301506 D15–11 –
Control Register
(16 bits)
D10
(REMC_INT)
D9
D8
D7–3 –
D2
D1
D0
0x302000–0x302094
Register name Address Bit
LCDC Interrupt 0x302000 D31–1 –
Enable Register
(32 bits)
(LCDC_INT) D0
Status and 0x302004 D31
Power Save
(32 bits) D30–8 –
Configuration
D7
Register
D6–2 –
(LCDC_PSAVE)
D1–0 PSAVE[1:0] Power save mode select
Horizontal 0x302010 D31–23 –
Display
(32 bits) D22–16 HTCNT[6:0] Horizontal total period (HT) setup
Register
(LCDC_HDISP)
D15–7 –
D6–0 HDPCNT
Vertical Display 0x302014 D31–26 –
Register
(32 bits) D25–16 VTCNT[9:0] Vertical total period (VT) setup
(LCDC_VDISP)
D15–10 –
D9–0 VDPCNT
MOD Rate 0x302018 D31–6 –
Register
(32 bits) D5–0 MOD[5:0]
(LCDC_MODR)
Horizontal 0x302020 D31–10 –
Display Start
(32 bits) D9–0 HDPSCNT
Position
Register
(LCDC_HDPS)
Vertical Display 0x302024 D31–10 –
Start Position
(32 bits) D9–0 VDPSCNT
Register
(LCDC_VDPS)
FPLINE Pulse 0x302028 D31–26 –
Setting Register
(32 bits) D25–16 FPLINE_
(LCDC_
FPLINE)
D15–8 –
D7
D6–0 FPLINE_
S1C33L26 TECHNICAL MANUAL
Name Function
reserved
reserved
(down counter)
reserved
REMDT Transmit/receive data
reserved
REMFIF
Falling edge interrupt flag
REMRIF Rising edge interrupt flag
REMUIF
Underflow interrupt flag
reserved
REMFIE
Falling edge interrupt enable
REMRIE Rising edge interrupt enable
REMUIE
Underflow interrupt enable
Name Function
reserved
FRINTEN Frame interrupt enable
FRINTF Frame interrupt flag
reserved
VNDPF Vertical display status flag
reserved
reserved
HT = HDP + HNDP
HT > HDPS + HDP (for HR-TFT)
reserved
Horizontal display period (HDP)
[6:0]
setup
reserved
VT = VDP + VNDP
VT > VDPS + VDP (for HR-TFT)
reserved
Vertical display period (VDP)
[9:0]
setup
reserved
LCD MOD rate setup
reserved
Horizontal display period start
[9:0] position for TFT
HT > HDP + HDPS + 1 (HR-TFT)
HT > HDP + HDPS (other TFT)
reserved
Vertical display period start posi-
[9:0]
tion for TFT
VT > VDP + VDPS
reserved
FPLINE pulse start position setup
ST[9:0]
reserved
FPLINE_ FPLINE pulse polarity setup
POL
FPLINE pulse width setup
WD[6:0]
Seiko Epson Corporation
APPENDIX A LIST OF I/O REGISTERS
Setting Init. R/W
–
0x0 to 0x3f 0x0 R/W
–
0x0 to 0x3f 0x0 R/W
0x0 to 0xff 0x0 R/W
–
1 1 (H) 0 0 (L)
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
LCD Controller (LCDC)
Setting Init. R/W
–
1 Enable 0 Disable
1 Occurred 0 Not occurred
–
1 VNDP 0 VDP
–
PSAVE[1:0] Mode 0x0 R/W
0x3 Normal
0x2 reserved
0x1 reserved
0x0 Power save
–
HT = (HTCNT + 1) × 8 [Ts]
0x0 R/W
HNDP = (HTCNT - HDPCNT)
× 8 [Ts]
–
HDP = (HDPCNT + 1) × 8 [Ts] 0x0 R/W
–
VT = VTCNT + 1 [lines] 0x0 R/W
VNDP = VTCNT - VDPCNT
[lines]
–
VDP = VDPCNT + 1 [lines] 0x0 R/W
–
0x0 to 0x3f 0x0 R/W
–
HDPS = HDPSCNT [Ts] 0x0 R/W 0x0 must be set for
–
VDPS = VDPSCNT [lines] 0x0 R/W 0x0 must be set for
–
0x0 R/W *1: For TFT
Start position =
FPLINE_ST + 1 [Ts]
–
1 Active high 0 Active low
Pulse width = 0x0 R/W
FPLINE_WD + 1 [Ts]
Remarks
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
0 R/W
Remarks
– – 0 when being read.
0 R/W
0 R/W Reset by writing 1.
– – 0 when being read.
1 R
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
STN panels.
– – 0 when being read.
STN panels.
– – 0 when being read.
0x0 must be set for
STN panels.
– – 0 when being read.
0 R/W (*1)
AP-A-51